sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-10-23	Fix bitmask (#346)	Angie Wang
	* toBitMask cat direction should be consistent with data * minor comment updates * moved remaining mem passes/utils to memlib * changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
2016-10-17	Reorganized memory blackboxing (#336)	Adam Izraelevitz
	* Reorganized memory blackboxing Moved to new package memlib Added comments Moved utility functions around Removed unused AnnotateValidMemConfigs.scala * Fixed tests to pass * Use DefAnnotatedMemory instead of AppendableInfo * Broke passes up into simpler passes AnnotateMemMacros -> (ToMemIR, ResolveMaskGranularity) UpdateDuplicateMemMacros -> (RenameAnnotatedMemoryPorts, ResolveMemoryReference) * Fixed to make tests run * Minor changes from code review * Removed vim comments and renamed ReplSeqMem
2016-09-25	Spec features added: AnalogType and Attach (#295)	Adam Izraelevitz
	* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-23	use .head instead of (0)	chick

2016-09-21	swap functions in MemPortUtils and MemTransformUtils properly for further ↵	Donggyu Kim
	refactoring
2016-09-13	Fix a lurking width-inference bug; improve adjacent style (#298)	Andrew Waterman
	ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)). I noticed this because of #297.
2016-09-13	use BoolType for UIntType(IntWidth(1))	Donggyu Kim

2016-09-13	use case object for Kind	Donggyu Kim

2016-09-13	type aliases	Donggyu Kim

2016-09-13	remove Utils.{width_BANG, long_BANG}	Donggyu Kim

2016-09-13	MemPortUtils: return correct memory types	Donggyu Kim

2016-09-13	clean up MemUtils	Donggyu Kim

2016-09-12	Change bitWidth to support ClockType	jackkoenig
	Match on GroundType instead of UIntType and SIntType
2016-09-06	Address style feedback and add tests for getConnectOrigin utility	Angie

2016-09-06	Support optionally filling write mask to data width via transform input ↵	Angie
	config file
2016-09-06	Changed wmask to convert from VecType to UInt	Angie
	* Instead of filling the whole data width * Added helper functions in MemUtils
2016-09-06	Corrected counting for VectorTypes in MemUtils	Angie
	* Was originally adding one extra set of things (to -> until) * MemPortUtil conditionally includes wmask, if necessary Changed endian-ness of write data/mask to match convention (little endian)
2016-09-06	Minor utility changes.	Angie
	* Corrected names to match current RW port spec * Added Jack's Namespace on Circuit
2016-08-18	Add MemUtils to aid in interfacing with alternate memory implementations (#244)	Albert Magyar