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path: root/src/main/scala/firrtl/passes/InferReadWrite.scala
AgeCommit message (Collapse)Author
2016-10-23Fix bitmask (#346)Angie Wang
* toBitMask cat direction should be consistent with data * minor comment updates * moved remaining mem passes/utils to memlib * changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
* Reorganized memory blackboxing Moved to new package memlib Added comments Moved utility functions around Removed unused AnnotateValidMemConfigs.scala * Fixed tests to pass * Use DefAnnotatedMemory instead of AppendableInfo * Broke passes up into simpler passes AnnotateMemMacros -> (ToMemIR, ResolveMaskGranularity) UpdateDuplicateMemMacros -> (RenameAnnotatedMemoryPorts, ResolveMemoryReference) * Fixed to make tests run * Minor changes from code review * Removed vim comments and renamed ReplSeqMem
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-25use sys.error instead of deprecated errorchick
2016-09-25implicit functions should specify return typechick
2016-09-23use .head instead of (0)chick
2016-09-21Fix clock connections in InferReadWrite (#310)Donggyu
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-21generalize Analysis.getConnects for code resuseDonggyu Kim
2016-09-13use case object for Kind (#267)Donggyu
use case object for Kind
2016-08-17Change RW port names (#236)Angie Wang
* Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch.
2016-08-02make infer readwrite ports optionalDonggyu Kim
turned on with '--inferRW <circuit name>'
2016-07-27infer readwrite ports for backward compatibilityDonggyu Kim
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