| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-02-23 | Add graph summation "+" to DiGraph (#744) | Schuyler Eldridge |
| 2018-02-07 | Fix EulerTour for circuits with one module (#736) | Schuyler Eldridge |
| 2018-01-15 | WiringTransform Refactor (#648) | Schuyler Eldridge |
| 2017-12-20 | Fix bug in ConstProp where module dependency edges were dropped (#696) | Jack Koenig |
| 2017-11-16 | Move digraph exceptions out of digraph class (#688) | Albert Magyar |
| 2017-11-10 | Make digraph methods deterministic (#653) | Albert Magyar |
| 2017-09-12 | Make pathsInDAG walk all possible paths (#655) | Schuyler Eldridge |
| 2017-07-14 | Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628) | Jack Koenig |
| 2017-04-03 | Find a single cycle from potentially many in a combinational SCC | Albert Magyar |
| 2017-03-30 | Change findSCCs to iterative implementation (#513) | Albert Magyar |
| 2017-03-17 | Add utilites for digraphs and netlist analyses | Albert Magyar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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