| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-05-13 | Add features.{LowerCaseNames, UpperCaseNames} transforms | Schuyler Eldridge | |
| Creates the features package and populates it with two new transforms: LowerCaseNames and UpperCaseNames. These transforms convert all names in a FIRRTL circuit to lower case or upper case. This is intended to help align generated Verilog with the policies of the company/institution using it. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add LowerCaseNames and UpperCaseNames transforms | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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