| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-11-19 | Disable random init (#2396) | Jiuyang Liu |
| 2021-10-28 | typo: correct Error Info (#2398) | SingularityKChen |
| 2021-08-02 | add emitter for optimized low firrtl (#2304) | Kevin Laeufer |
| 2021-07-29 | Dedup attribute annos (#2297) | Jared Barocsi |
| 2021-07-14 | Fix memory annotation deduplication (#2286) | Jared Barocsi |
| 2021-04-19 | Don't use declaration-assigns for wires representing mem ports (#2189) | Albert Magyar |
| 2021-04-05 | Allow direct emission of sync-read memories to Verilog | Albert Magyar |
| 2021-04-01 | Add memory initialization options for synthesis (#2166) | Carlos Eduardo |
| 2021-03-16 | Fix issue where inlined cvt could cause crash (#2124) | Jack Koenig |
| 2021-03-09 | Fix the readmem statements in nested block (#2109) | Carlos Eduardo |
| 2021-03-09 | Create annotation to allow inline readmem in Verilog (#2107) | Carlos Eduardo |
| 2021-02-25 | Emit space after 'if' for all Verilog conditional synchronous assignments (#2... | Albert Magyar |
| 2020-11-10 | Refactor emiter (#1879) | Jiuyang Liu |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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