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* Remove LegacyAnnotation and MoultingYaml
It has been deprecated since 1.1
* Remove all uses of ConvertLegacyAnnotations
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add CleanupNamedTargets Transform
Adds a new transform, CleanupNamedTargets, that will convert
ReferenceTargets to InstanceTargets if any ReferenceTargets are found
to be actually pointing at instances.
This fixes an issue where a ComponentName pointing at an instance will
be converted to a ReferenceTarget. Later on, this ReferenceTarget will
not be properly renamed by other transforms, e.g.,
EliminateTargetPaths.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Update ScalaTests
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* InstanceKeyGraph: add staticInstanceCount, getGraph and getChildrenInstanceMap
* InstanceKeyGraph: reachableModules, unreachableModules, lowestCommonAncestor and fullHierarchy
* Replace usage of InstanceGraph with InstanceKeyGraph
Also deprecates all unused methods.
* WiringUtils: make new version of sinksToSources package private
This will make our live easier next time we need to change it.
* CircuitGraph: use InstanceKeyGraph
* InstanceKeyGraphSpec: respect maximum line width
* InstanceKeyGraph: make constructor private
* InstanceKeyGraph: move lowestCommonAncestor function to Wiring
* WiringUtils: update deprecation message
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* WIP Commit
* Add EdgeDataDiGraph with views to amortize graph construction
* WIP, got basic structure, need tests to pipeclean
* First tests pass. Need more.
* Tests pass, more need to be written
* More tests pass! Things should work, except for memories
* Added clearPrev to fix digraph uses where caching prev breaks
* Removed old Component. Documented IRLookup
* Added comments. Make prev arg to getEdges
* WIP: Refactoring for CircuitGraph
* Refactored into CircuitGraph. Can do topological module analysis
* Removed old versions
* Added support for memories
* Added cached test
* More stufffff
* Added implicit caching of connectivity
* Added tests for IRLookup, and others
* Many major changes.
Replaced CircuitGraph as ConnectionGraph
Added CircuitGraph to be top-level user-facing object
ConnectionGraph now automatically shortcuts getEdges
ConnectionGraph overwrites BFS as PriorityBFS
Added leafModule to Target
Added lookup by kind to IRLookup
Added more tests
* Reordered stuff in ConnectionGraph
* Made path work with deep hierarchies. Added PML for IllegalClockCrossings
* Made pathsInDAG work with current shortcut semantics
* Bugfix: check pathless targets when shortcutting paths
* Added documentation/licenses
* Removed UnnamedToken and related functionality
* Added documentation of ConnectionGraph
* Added back topo, needed for correct solving of intermediate modules
* Bugfix. Cache intermediate clockSources from same BFS with same root, but not BFS with different root
* Added literal/invalid clock source, and unknown top for getclocksource
* Bugfix for clocks in bundles
* Add CompleteTargetSerializer and test
* remove ClockFinder, be able to compile.
* test is able to compile, but need to fix.
* public and abstract DiGraph, remove DiGraphLike.
* revert some DiGraph code, ConnectionGraphSpec passed.
* CircuitGraphSpec passed.
* minimize diff between master
* codes clean up
* override linearize and revert DiGraph
* keep DiGraph unchanged.
* make ci happy again.
* codes clean up.
* bug fix for rebase
* remove wir
* make scaladoc happy again.
* update for review.
* add some documentation.
* remove tag
* wip IRLookup
* code clean up and add some doucmentations.
* IRLookup cache with ModuleTarget guarded.
* make unidoc and 2.13 happy
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Support Memory Initialization for Simulation and FPGA Flows
This adds a minimal annotation that allows users to
influence if memories are randomly initialized,
if all entries are initialized to the same scalar or
if each entry should be initialized to a different value.
We use the init block in order to initialize memories
which is supported by verilator as well as yosys
and has previously been used to randomize the initial
memory contents.
* LowerTypes: error when trying to split up a memory with MemoryInitAnnotation
Currently the MemoryInitAnnotation only works for
ground-type memories.
We catch misuse of this annotation at the point of
the firrtl compiler at which memories on non-ground type
get split up, i.e., the LowerTypes transform.
Chisel should try to prevent annotating non-ground
type memories in the frontend, but it is nice to
have an additional check.
* MemoryInitSpec: test JSON deserialization
* MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- RenameMap Behavior
-- Prevent transitive renaming A -> B -> C (continueRenaming)
-- Prevent transitive renaming for self-renames
- Target
-- Override toString as serialize for CompleteTarget
-- Expansion of stripHierarchy to enable stripping InstanceTargets to become ModuleTargets
Annotations
-- Bugfix in extractComponents where Products were not iterated over
-- Converts renamed targets to local targets using Target.referringModule to preserve sticky behavior
- Eliminate Target Paths
-- Make DuplicationHelper use LinkedHashMap, as we iterate over its contents and convert to Seq in def makePathless
-- Add DupedResult to map original module to new module targets
-- Update renaming to record a map from all relative instance paths to original module, to new module target
-- Consumes DedupedResult to give better name to new duplicated module if it was originally deduplicated
-- Reorder modules in attempt to preserve original ordering, pre-deduplication
-- Move utility functions to object
-- Bugfix: add self-renames to prevent ofModule _ of target _ cannot be renamed to Vector(_, _, _, ...) errors
- Dedup
-- Changed NoDedupAnnotation to contain ModuleTarget, rather than ModuleName
-- Added DedupedResult to map original module to the duplicate module
-- Consumes DupedResult to pick better name, if it existed
-- Updates renaming to chain the following: instancify deduped modules, remap differently named internal signals, then remap AST modules
-- Move utility functions to object
-- Remove annotations as part of determination of dedup correctness
-- Bugfix: add instance renames so that deduped modules have their instances properly renamed
- Dead Code Elimination
-- Add deletion of ASTModules
- Tests
-- Morphism Spec to ensure Dedup -> EliminateTargetPaths and EliminateTargetPaths -> Dedup patterns work properly
-- Update existing tests to make sure they work properly
-- Add Dedup tests to demonstrate instance renaming bug, EliminateTargetPaths for ofModule rename bug, and update RenameMap tests
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Absorb WRef into Reference
* Absorb WSubField into SubField
* Absorb WSubIndex into SubIndex
* Absorb WSubAccess into SubAccess
* Absorb WDefInstance into DefInstance
------------------------- API CHANGE SEVERITY --------------------------
This is projected to not break source-level compatibility with any known
user code. However, it will break *binary* compatibility with all
existing user FIRRTL passes, as is generally allowed with major
releases of FIRRTL.
--------------------------- DESCRIPTION --------------------------------
Previously, there were several nodes in WIR.scala that had a one-to-one
correspondance with existing nodes in the standard firrtl.ir hierarchy.
These nodes would have a case class resembling the corresponding
standard IR node, but with the addition of one or more "analysis"
fields.
Since these fields (such as kind) represent helpful info that can be
invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not
cause any issues to simply include these fields on any in-memory
representation of FIRRTL IR. Although other systems for tracking FIRRTL
analyses have evolved over time, the ubiquity of pattern-matching on
these fields has lead most core and custom transforms to be written
against WIR, rather than IR.
This PR unifies the IRs by adding the fields that would be in an
"augmented" WIR node directly into the corresponding IR node; i.e., the
"type" and "kind" fields from WRef are added directly to the definition
of the Reference case class, while these "repetitive" WIR case classes
are removed entirely.
-------------------- SOURCE-COMPATIBILITY ADAPTERS ---------------------
Several object methods are added to WIR.scala to maintain
source-compatiblity for passes that used WIR. These objects define
factory methods and unapply methods, so passes that relied on implicit
case class factories or pattern matching for the removed WIR types will
remain perfectly source-compatible. However, these do not guarantee
compatibility at the binary level.
The types of the removed WIR case classes are also added as type aliases
to the top-level firrtl package, which allows code that relies on
explicit constructor calls or reflection to retain source-compatibility.
Finally, additional explicit factory methods are added to the companion
objects of the newly-augmented IR case classes, which allows user code
to avoid having to specify any of the new analysis fields. Existing code
that created non-WIR IR nodes will be able to continue using the
previous factory signatures, which will cause all omitted analysis
fields to be set to Unknown.
---------------------- UNMITIGATED API CHANGES -------------------------
While passes that used WIR will be source-compatible with this change,
there is one significant change that affects any pass currently using
non-WIR IR: the signatures of pattern-matching cases for Reference,
SubField, SubIndex, SubAccess, and DefInstance must change to
accommodate the extra fields.
This cannot be worked at the API level due to restrictions on unapply
overloading, but it could theoretically be solved with macros or other
static rewriting. However, only four core transforms (RemoveProto,
ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is
expected that no user code currently relies on it, so the expected
migration strategy is simply to change the small fraction of code
relying on these nodes.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This mixes in the new DependencyAPIMigration trait into all Transforms
and Passes. This enables in-tree transforms/passes to build without
deprecation warnings associated with the deprecated CircuitForm.
As a consequence of this, every Transform now has UnknownForm as both
its inputForm and outputForm. This PR modifies legacy Compiler and
testing infrastructure to schedule transforms NOT using
mergeTransforms/getLoweringTransforms (which rely on inputForm and
outputForm not being UnknownForm), but instead using the Dependency
API.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* EliminateTargetPaths: add lone instance test cases
* EliminateTargetPaths: don't rename lone instances
* get rid of trailing comma
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* update JsonProtocolSpec to test GroundType
* add custom serializer for GroundType
* get rid of trailing comma
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Eliminate warnings on `sbt doc` and `sbt unidoc`
- removed toFirrtl reference on MultiTargetAnnotation
- lots of places where package path has to be added to comment references
- Change to use `/** text starts here` convention when wrong in comment with a doc fix.
- Did not exhaustively change these
- Wrestled doc example in RenderDiGraph#renderNode, not sure if I won
- Cleaned up InferWidths & CatchExceptions imports
- Added missing license message to a couple of files.
- fixed a couple of stale parameter names in scaladoc
- Added @unchecked to stop erasure warning in Emitting where emission annotations are collected
- Change types to [_] on match in RenameMap#recordAll to fix erasure warning
* Where possible change [[firrtl.ir.X]] to [[firrtl.ir.X X]] for better display in scaladoc
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Remove toNamed (and friends) deprecation.
* Add inadvertently deleted leading double quote.
* Remove commented out deprecations.
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* Change from log-level debug to trace
* Serialize as JSON rather than .serialize on each annotation
Co-Authored-By: Chick Markley <chick@qrhino.com>
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Introduce Preset Register Specialized Emission
- Introduce EmissionOption trait
- Introduce PresetAnnotation & PresetRegAnnotation
- Enable the collection of Annotations in the Emitter
- Introduce collection mechanism for EmissionOptions in the Emitter
- Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
- Add corresponding tests spec and tester
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add firrtl-json serializers
* Added support for ports, info. Added docs and tests
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Change the behavior of EliminateTargetPaths to generate ModuleTarget
renames when instances are duplicated. Previously, only InstanceTarget
renames would be generated.
In effect, annotations targeting a duplicated module when be
duplicated to point at the original and duplicated module.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a utility method, referringModule, to the Target object that
behaves like IsMember.pathlessTarget except that it returns the module
of an InstanceTarget. This is useful for situations where you want to
get at "the module" a target is pointing at, but you want behavior
to get an actual module from an instance.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Change EliminateTargetPaths to remove ResolvePaths annotations in the
output AnnotationSeq. This prevents a bug whereby the upstream
ResolvePaths annotations from previous runs of EliminateTargetPaths
can result in unexpected duplication.
Adds a test that checks that ResolvePaths annotations are actually
removed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This changes uses of `getSimpleName` to `getName`. The former throws
idiotic exceptions under Java 8, e.g., `getSimpleName` will fail if
used on a class inside an object.
This fixes a bug where any call to the `name` method of a custom
transform defined inside an object (or in an environment wrapping
things in objects like a REPL) will throw a malformed class name
exception. E.g., if you do this and run with `-ll info` or your custom
transform deletes annotations.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: Jack Koenig <koenig@sifive.com>
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Major features:
- Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz.
- Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp
- Refactored width/bound inferencer into a separate constraint solver
- Added transforms to infer, trim, and remove interval bounds
- Tests for said features
Plan to be released with 1.3
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(#1186)
* Replace instance analysis code with InstanceGraph API calls
* Add convenience implicits for using TargetTokens as safe boxed strings
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* add multi target annotation for advices
* use Seq[Seq[Target]] store targets
* add flat function
* doc simplify
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* check isLocal before removing target tokens in RenameMap
* add fix for Adam's test case, add more test cases
* fix multiple renaming bug
* call componentGet before checking underlying for ReferenceTargets in recursiveGet
* add ModuleGet that implements new instance rename order
* normalize target before renaming
* fix forall/exists bug
* add guards for isLocal cases
* fix circuit renaming, fix traverseHierarchy, add debug prints
* remove sensitivity stuff
* add more tests
* reapply parent path to renamed subpath, fix reference -> instance renames
* remove debug prints
* add instance as reference test case
* fix Ref->IsMod, IsMod->Ref renamed, fix extra test cases
* fix ofModule renaming for refs/instances
* fix renaming of ofModules, change tests
* fix more InstanceTarget rename bugs
* remove bad ReferenceTarget test case
* cleanup midRename of recursiveGet
* fix comments
* fix multiple ModuleTarget renames for InstanceTargets
* dis-allow renaming of ModuleTargets to References
* add back removed lines in RemoveCHIRRTL
* fix indents
* only add ofModule to refs if renaming an inst as a ref
* change .moduleOpt.get to .module
* disallow renaming ReferenceTarget->ModuleTarget
* disallow ref->mod renames in tests, add inst as ref test cases
* cache results of get functions
* fix bot/mid/top renames, add andThen
* fix andThen, add test case
* add more test cases, fix ++
* fix comments, make things private
* dont quit if earlier returns None, add dedup/inline rename tests
* don't rename OfModules to instances paths
* update dedup test
* don't treat references as instances, don't reapply parents to absolute paths
* fix more test cases
* short-circuit OfModule renames if an absolute path is found
* update andThen, remove orElse, deprecate ++
* removed commented code
* update comments
* respond to comments
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* Add sbt-scalafix
* Add scalafix guide to README
* Remove Unused Import
* Remove deprecated procedure syntax
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This adds FirrtlStage, a reimplementation of the original FIRRTL
Driver as a Stage. This updates the original firrtl.options package to
implement FirrtlStage (namely, TransformLike is added) along with
FirrtlMain. Finally, the original FIRRTL Driver is converted to a
compatibility wrapper around FirrtlStage.
For background, Stage and Phase form the basis of the Chisel/FIRRTL
Hardware Compiler Framework (HCF). A Phase is a class that performs a
mathematical transformation on an AnnotationSeq (in effect, a
generalization of a FIRRTL transform). Curtly, a Stage is a Phase that
also provides a user interface for generating annotations. By their
construction, Phases are designed to be composed sequentially into a
transformation pipeline.
This modifies the existing options package (which provides
Stage/Phase) to build out a type hierarchy around Stage/Phase. This
adds TransformLike[A] which implements a mathematical transformation
over some type A. Additionally, and as an interface between different
TransformLikes, this adds Translator[A, B] which extends
TransformLike[A], but does an internal transformation over type B.
This is used to interface Phases with the existing FIRRTL compiler.
This adds a runTransform method to Phase that, like
Transform.runTransform, will automatically detect deleted Annotations
and generate DeletedAnnotations.
The new FirrtlStage, a reimplementation of FIRRTL's Driver, is added
as a Stage composed of the following Phases:
1. AddDefaults - add default annotations
2. AddImplicitEmitter - adds an implicit emitter derived from the
compiler
3. Checks - sanity check the AnnotationSeq
4. AddCircuit - convert FIRRTL input files/sources to circuits
5. AddImplicitOutputFile - add a default output file
6. Compiler - run the FIRRTL compiler
7. WriteEmitted - write any emitted modules/circuits to files
The Driver is converted to a compatibility layer that replicates old
Driver behavior. This is implemented by first using new toAnnotation
methods for CommonOptions and FirrtlExecutionOptions that enable
AnnotationSeq generation. Second, the generated AnnotationSeq is
preprocessed and sent to FirrtlStage. The resulting Phase order is
then:
1. AddImplicitAnnotationFile - adds a default annotation file
2. AddImplicitFirrtlFile - adds a default FIRRTL file using top name
3. AddImplicitOutputFile - adds an output file from top name
4. AddImplicitEmitter - adds a default emitter derived from a
compiler and any split modules command line option
5. FirrtlStage - the aforementioned new FirrtlStage
Finally, the output AnnotationSeq is then viewed as a
FirrtlExecutionResult. This compatibility layer enables uninterrupted
usage of old Driver infrastructure, e.g., FirrtlExecutionOptions and
CommonOptions can still be mutated directly and used to run the
Driver.
This results in differing behavior between the new FirrtlStage and the
old Driver, specifically:
- FirrtlStage makes a clear delineation between a "compiler" and an
"emitter". These are defined using separate options. A compiler is
"-X/--compiler", while an emitter is one of "-E/--emit-circuit" or
"-e/--emit-modules".
- Related to the above, the "-fsm/--split-modules" has been removed
from the FirrtlStage. This option is confusing once an implicit
emitter is removed. It is also unclear how this should be handled
once the user can specify multiple emitters, e.g., which emitter
should "--split-modules" apply to?
- WriteOutputAnnotations will, by default, not write
DeletedAnnotations to the output file.
- The old top name ("-tn/--top-name") option has been removed from
FirrtlStage. This option is really a means to communicate what
input and output files are as opposed to anything associated with
the circuit name. This option is preserved for the Driver
compatibility layer.
Additionally, this changes existing transform scheduling to work for
emitters (which subclass Transform). Previously, one emitter was
explicitly scheduled at the end of all transforms for a given
compiler. Additional emitters could be added, but they would be
scheduled as transforms. This fixes this to rely on transform
scheduling for all emitters. In slightly more detail:
1. The explicit emitter is removed from Compiler.compile
2. An explicit emitter is added to Compiler.compileAndEmit
3. Compiler.mergeTransforms will schedule emitters as late as
possible, i.e., all emitters will occur after transforms that
output their input form.
4. All AddImplicitEmitter phases (DriverCompatibility and normal)
will add RunFirrtlTransformAnnotations to add implicit emitters
The FIRRTL fat jar utilities are changed to point at FirrtlStage and not
at the Driver. This has backwards incompatibility issues for users
that are using the utilities directly, e.g., Rocket Chip.
The Logger has been updated with methods for setting options based on
an AnnotationSeq. This migrates the Logger to use AnnotationSeq as
input parameters, e.g., for makeScope. Old-style methods are left in
place and deprecated. However, the Logger is not itself a Stage.
The options of Logger Annotations are included in the base Shell and
Stage is updated to wrap its Phases in a Logger scope.
Additionally, this changes any code that does option parsing to always
prepend an annotation as opposed to appending an annotation. This is
faster, but standardizing on this has implications for dealing with
the parallel compilation annotation ordering.
A Shell will now put the initial annotations first (in the order the
user specified) and then place all annotations generating from parsing
after that. This adds a test case to verify this behavior.
Discovered custom transforms (via `RunFirrtlTransformAnnotation`s) are
discovered by the compiler phase in a user-specified order, but are
stored in reverse order to more efficiently prepend (as opposed to
append) to a list. This now reverses the transform order before
execution to preserve backwards compatibility of custom transform
ordering.
The Compiler phase also generates one deleted annotation for each
`RunFirrtlTransformAnnotation`. These are also reversed.
Miscellaneous small changes:
- Split main method of Stage into StageMain class
- Only mix in HasScoptOptions into Annotation companion objects (h/t
@jackkoenig)
- Store Compiler in CompilerAnnotation
- CompilerNameAnnotation -> CompilerAnnotation
- Make Emitter abstract in outputSuffix (move out of FirrtlOptions)
- Add DriverCompatibility.AddImplicitOutputFile that will add an
output file annotation based on the presence of a
TopNameAnnotation. This is important for compatibility with the
old Driver.
- Cleanup Scaladoc
- Refactor CircuitOption to be abstract in "toCircuit" that converts
the option to a FirrtlCircuitAnnotation. This allows more of the
conversion steps to be moved out of AddCircuit and into the actual
annotation.
- Add WriteDeletedAnnotation to module WriteOutputAnnotations
- A method for accessing a FirrtlExecutionResultView is exposed in
FIRRTL's DriverCompatibilityLayer
- Using "--top-name/-tn" or "--split-modules/-fsm" with FirrtlStage
generates an error indicating that this option is no longer
supported
- Using FirrtlStage without at least one emitter will generate a
warning
- Use vals for emitter in Compiler subclasses (these are used to
build RunFirrtlTransformAnnotations and the object should be
stable for comparisons)
- Fixes to tests that use LowTransformSpec instead of
MiddleTransformSpec. (SimpleTransformSpec is dumb and won't
schedule transforms correctly. If you rely on an emitter, you need
to use the right transform spec to test your transform if you're
relying on an emitter.)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation
Add custom LoadMemoryFileTypeSerializer.
Add test to verify LoadMemoryAnnotation can be correctly serialized/deserialized.
* Simplify and focus LoadMemoryAnnotation serialization/deserialization.
Respond to comments on earlier implementations.
* Add type FileType definition for current chisel3 code.
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This fixes all Scaladoc warnings except for those trying to link to
Java.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos
* add test cases
* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos
* remove println
* cleanup tests
* remove extraneous constraints
* use foreachStmt instead of mapStmt
* remove support for aggregates
* fold InferWidthsWithAnnos into InferWidths
* throw exception if ref not found, check for annos before AST walk
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* Correctly handle dots in loaded memory paths
* Added test for loadmem filename
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