| Age | Commit message (Collapse) | Author |
|---|
|
This fixes all Scaladoc warnings except for those trying to link to
Java.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
|
|
* Correctly handle dots in loaded memory paths
* Added test for loadmem filename
|
|
- Fixed edge case file name that starts with . and has no suffix
|
|
* Support for load memory annotations in chisel
This PR
* Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
* remove from VerilogCompiler
* move to VerilogEmitter
* Changes the verilog emitter to allow programmatic access to the verilog module declaration
* Creating a bindable module requires headers to match
* Provides a unit test that shows how to generate a bindable module.
* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading
* Binding support
- Fixed bug that handled suffixes on memory initializing files
* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer
|
