aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/WIR.scala
AgeCommit message (Collapse)Author
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2019-02-04Correct Kind info from #1010 (#1012)Albert Magyar
2019-02-01Mem helpers (#1010)Albert Magyar
* Add memory WRef factory for completeness * Refactor DefAnnotatedMemory construction for clarity
2019-01-23Improve Shl codegen; eliminate Shlw WIR node (#994)Andrew Waterman
* Improve Shl codegen; eliminate Shlw WIR node If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's no need for Verilog-specific padding in the PadWidths pass. Avoiding the redundant padding improves compiler/simulator performance and renders Shlw unnecessary. * [skip formal checks] Add test
2018-12-21Small convenience tweaks to IR/WIR APIs (#961)Albert Magyar
* Seal Direction trait * Add WRef factories for ports and instances
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
* Added Foreachers * Changed CheckTypes to use foreach * Check widths now uses foreach * Finished merge, added foreachers to added stmts * Address reviewer feedback
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
Fixes a bug where registers could be instantiated after nodes that referred to them Also add WRef.apply utility for nodes
2018-06-28Protobuf (#832)Jack Koenig
Add support for ProtoBuf serialization and deserialization * Add support for additional features in .proto description Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params * Add support for .pb input files This involves an API change where FIRRTL no longer implicitly adds .fir to input file names
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
* Added grouping pass * Added InfoMagnet and infomappers * Changed return type of execute to allow final CircuitState inspection * Updated dedup. Now is name-agnostic * Added GroupAndDedup transform
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation. Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed. This transform preserves deduplication. All instances of a given DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-02-23move more general utils out of memutils, mov WIR helpers to WIR.scala and ↵Angie
update uses
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
* Rework Attach to work on arbitrary Analog hierarchies If there are zero or one Analog sources in an Attach (source meaning wire or parent module port), then the Attach will be emitted as a simple point to point connection. In the general case, alias is used for simulation while forwards and backwards assigns for synthesis. Verilator does not currently support the general case so an `ifdef Verilator `error is emitted. * Add helper functions for creating WRef from Reg and Wire
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-23use .head instead of (0)chick
2016-09-14fix spaces in WIR.scalaDonggyu Kim
2016-09-13use case object for WVoid, WInvalidDonggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-12Rework map functions as class methodsjackkoenig
Changed code from match statements in Mappers.scala to methods on the various IR classes. This allows custom IR nodes to implement the mapper functions and thus work (ie. not match error) when map is called on them. This also should have a marginal performance increase because of use of virtual function calls rather than match statements.
2016-09-07clean up WIR.scalaDonggyu Kim
2016-09-06optimize equals of WrappedExpression & WrappedTypeDonggyu Kim
2016-08-02Change serialize to abstract method on FirrtlNodeJack Koenig
2016-06-10API Cleanup - ASTJack
trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-06-10API Cleanup - PrimOp & PrimOpsJack
Add simple documentation trait PrimOp -> abstract class PrimOp Move PrimOp case objects to object PrimOps Rename PrimOp case objects to match concrete syntax Overrwrite toString for more canonical serialization Update some PrimOps utility functions
2016-06-10API Cleanup - ExpressionJack
trait Expression -> abstract class Expression Ref -> Reference abbrev. exp -> expr Add abstract class Literal UIntValue -> UIntLiteral extends Literal SIntValue -> SIntLiteral extends Literal
2016-06-10API Cleanup - StatementJack
trait Stmt -> abstract class Statement (to match Expression) abbrev. exp -> expr BulkConnect -> PartialConnect camelCase things that were snake_case case class Empty() -> case object EmptyStmt Change >120 character Statements to multiline
2016-06-10API Cleanup - WidthJack
Add simple documentation trait Width -> abstract class Width case class UnknownWidth -> case object UnknownWidth
2016-06-10API Cleanup - TypeJack
trait Type -> abstract class Type case class ClockType() -> case object ClockType case class UnknownType() -> case object UnknownType Add GroundType and AggregateType ClockType has width of IntWidth(1)
2016-05-10Added pad widths to eliminate all implicit width extendingAdam Izraelevitz
2016-05-03Move splitRef and mergeRef from LowerTypes to Utilsjackkoenig
Make EmptyExpression part of WIR
2016-05-03Add HasInfo trait to IR, IsDeclaration mixes in HasInfojackkoenig
Change Field from IsDeclaration to HasName Make WDefInstance an IsDeclaration
2016-04-21Add Expression.tpe accessorAndrew Waterman
Almost all of the code was already there. This is cleaner (and faster) than calling tpe(Expression).
2016-04-09Fix bundle type equalityAdam Izraelevitz
Was not checking for length of bundles, so if the bundles matched but one had more fields, it was not caught.
2016-02-25Separate serialize functions into separate filejackkoenig
2016-02-25Remove FlagUtils and related unused debug printingjackkoenig
2016-02-09Added license to FIRRTL filesazidar
2016-02-09CHIRRTL passes work, parser is updatedazidar
2016-02-09Added chirrtl passes, need to update parserazidar
2016-02-09More bug fixesazidar
2016-02-09Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ↵azidar
rocketchip
2016-02-09Added Lower Types.azidar
2016-02-09Added Expand Whens passazidar
2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09WIP. Finished to working ir, resolve kinds, and infer typesazidar
2016-02-09WIP. Got to-working-ir workingazidar
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-03 16:42:23 +0000