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If 'import FIRRTLParser._' globally, 'FIRRTLParser.' is unnecessary.
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Use getWidth function if it is suitable.
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Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
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* Update Parser to use ANTLR CharStreams
This removes some unnecessary object creation in String reading and
manipulation
* Remove two unnecessary traversals from Block construction in Visitor
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Escape raw params using \'
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Also minor cleanup to literal construction in Visitor
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* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
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Refactor StringLit to use String instead of Array[Byte]
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* Update dependencies and JavaConverters for Scala 2.12
* Bump Scala (and library) version(s).
* replace "error" with "Utils.error"; bump Scala version to 2.11.11
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SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
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Workaround for #470. This allows parsing DoubleLits in subfield
expressions.
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Also remove parsing support for ids with characters not supported in
Verilog nor in the Firrtl spec
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* Rework Attach to work on arbitrary Analog hierarchies
If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.
* Add helper functions for creating WRef from Reg and Wire
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.
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Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.
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* WIP: Adding FixedType to Firrtl proper
Got simple example running through width inference
Checks should be ok
Need to look into FixedLiteral more
* Added simple test for fixed types
* Added asFixedPoint to primops
* Added tail case for FixedType
* Added ConvertFixedToSInt.scala
Added pass to MiddleToLowerFirrtl transform
* Replace AsFixedType with AsSInt in fixed removal
* Bugfix: constant from asFixed not deleted
* Added unit test for bulk connect
* Fixed partial connect bug #241
* Fixed missing case for FixedPoint in legalizeConnect
* Add FixedMathSpec that demonstrates some problems with FixedPointMath
* Fixed test and ConvertToSInt to pass.
Negative binary points not easily supported, needs much more time to
implement.
* Refactored checking neg widths
Make checking for negative binary points easier
* Added tests for inferring many FixedType ops
shl, shr, cat, bits, head, tail, setbp, shiftbp
* Handle bpshl, bpshr, bpset in ConvertFixedToSInt
Changed name from shiftbp -> bpshl, bpshr
Change name from setbp -> bpset
Added more tests
* Added set binary point test that fails
* Added simple test for zero binary point
* gitignore fixes for antlr intermediate dir and intellij dir
* removed unused imports
retool the fixed point with zero binary point test
* simplified example of inability to set binary point to zero
* Temporary fix for zero-width binary point
This fix allows for all widths to be zero, but since this is a feature I
am working on next, I'm not going to bother with a more stringent check.
* change version for dsp tools
* Removed extra temporary file
* Fixed merge bug
* Fixed another merge bug
* Removed commented out/unrelated files
* Removed snake case
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* Spec features added: AnalogType and Attach
AnalogType(width: Width):
- Concrete syntax:
wire x: AnalogType<10>
- New groundtype, very restricted in use cases.
- Can only declare ports and wires with Analog type
- Analog types are never equivalent, thus if x and y have Analog
types: x <= y is never legal.
Attach(info: Info, source: Expression, exprs: Seq[Expression]):
- Concrete syntax:
attach x to (y, z)
- New statement
- Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
- Exprs must have an Analog type reference an instance port
- Source and exprs must have identical widths
Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.
* Fixed bug where invalidated ports aren't handled
* Bugfix for VerilogPrep
Intermediate wires for invalidated instance ports were not invalidated
* Bugfix: calling create_exp with name/tpe
Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals
* Addressed donggyukim's style comments
* Reworked pass to only allow analog types in attach
Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)
* Fixup bugs from pulling in new changes from master
* comments for type eqs and small style fixes
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example 1 s"${x}"
example 2 case blah => { ??? }
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Indentation support for the ANTLR parser
- some clean-up of the parser code (TODO: file input could be improved, more clean-up)
- get rid of Translator and specify all syntactic rules in antlr4 grammer
- support for else-when shorthand in the grammar
- rename Begin to Block which makes more sense
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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trait Expression -> abstract class Expression
Ref -> Reference
abbrev. exp -> expr
Add abstract class Literal
UIntValue -> UIntLiteral extends Literal
SIntValue -> SIntLiteral extends Literal
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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Add simple documentation
trait Width -> abstract class Width
case class UnknownWidth -> case object UnknownWidth
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Add simple documentation
Flip -> Orientation
trait Orientation -> abstract class Orientation
Orientation case objects to upper camel case
REVERSE -> Flip
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trait Type -> abstract class Type
case class ClockType() -> case object ClockType
case class UnknownType() -> case object UnknownType
Add GroundType and AggregateType
ClockType has width of IntWidth(1)
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Add simple documentation
Change Direction case objects to upper camel case
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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easier testing, because we don't the source locator information to say a test fails
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Fixes ucb-bar/chisel3#87
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IntLits (all IntLits handled by Parser and Visitor the same, checks come later), also delete first and last char of string literals since those characters are the quotes.
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for the Parser. Added custom Parser exceptions for better error reporting and checking. Fixed bug in grammar not allowing most keywords as Ids
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accordingly
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