| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-28 | WIP Added support for is invalid and validif to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP Added support for stop to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP Added support for printf to Scala FIRRTL | jackkoenig |
| 2016-01-28 | WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTL | jackkoenig |
| 2016-01-27 | WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented (n... | jackkoenig |
| 2015-12-03 | Changing simwrapper to group ports that go to different places, not quite the... | jackkoenig |
| 2015-10-15 | Reorganized Primops (renamed from PrimOps), added maps and functions to conve... | Jack |
| 2015-10-12 | Renamed Subindex to Index and added type information to Index and DoPrimOp | Jack |
| 2015-10-12 | Added support for no width to mean unknown, and print nothing instead of <?> ... | Jack |
| 2015-10-02 | Merged in Scala implementation of FIRRTL IR, parser, and serialization (ie. A... | Jack |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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