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path: root/src/main/scala/firrtl/Utils.scala
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2018-11-26Make return types of util functions more specific (#949)Albert Magyar
2018-10-31Remove all uses of get_flip and deprecateJack Koenig
It is O(n) and every use is in an O(n) iteration resulting in O(n^2). Same information can be extracted from create_exps which happens to also be called at every use of get_flip.
2018-10-31Speed up create_exps by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-30Instance Annotations (#926)Adam Izraelevitz
Formerly #865 Major Code Changes/Features Added: Added Target trait as replacement for Named Added TargetToken as token in building Target Added GenericTarget as a catch-all Target Added CircuitTarget, ModuleTarget, ReferenceTarget, and InstanceTarget Added ResolvePaths annotation Added EliminateTargetPaths (and helper class DuplicationHelper) Updated Dedup to work with instance annotations Updated RenameMap to work with instance annotations DCE & ConstantProp extend ResolveAnnotationPaths
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
This reverts commit 7e2f787e125227dc389d5cf1d09717748ecfed2e.
2018-10-24Instance Annotations (#865)Adam Izraelevitz
Added Target, which now supports Instance Annotations. See #865 for details.
2018-09-27Add Utils.expandPrefixes as Prefix Unique helper (#900)Schuyler Eldridge
This adds a utility, expandPrefixes, that expands a string into all possible prefixes based on a delimiter. Any repeated occurrence of the delimiter is viewed as a contributing to a prefix. E.g., "foo_bar" expands to Seq("foo_", "foo_bar"). This is useful for inlining and keyword mangling on LowForm. You would like to be able to generate a new name that is prefix unique with respect to a namespace. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
Also minor cleanup to literal construction in Visitor
2018-04-13Remove infinitely recursive function (#790)Jack Koenig
h/t @sdtwigg
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, ↵Adam Izraelevitz
but not Emitter. (#717)
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
* Catch exceptions and convert to internal error. We need to update the displayed message to incorporate a line number and text to be used for the issue. * Cleanup exception handling/throwing. Re-throw expected (or uncorrectable exceptions). Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain. Update tests to conform to FreeSpec protocol. * Minor cleanup Admit we've updated some deprecated ScalaTest methods.
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
[skip formal checks] Generate nicer name for remove accesses
2017-12-20Add "checker" to the set of Verilog keywords - fixes 455. (#711)Jim Lawson
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
* Update dependencies and JavaConverters for Scala 2.12 * Bump Scala (and library) version(s). * replace "error" with "Utils.error"; bump Scala version to 2.11.11
2017-05-18Upgrade Logging facility (#488)Chick Markley
* Upgrade Logging facility Make thread-safe Make logging by package name work Use caching of class names to level for performance Make some tests to show this working * quick fix for dynamic logging variable * A number of changes based on Adam's suggestions Default LoggerState But there is an invoke method now to handle threading issues. This should be propagated to other projects Driver.execute methods * Add built-in support for string capture of Logging * Usability fixes for logging stuff. Settings made to the logger prior to execute/invoke will be passed along if possible. * A couple style fixes Comment and privatize Logger state * Name and save string buffers used for logging * Fix default logging state setting Fix logging test, did not have change to command argument * comment out logging in InlineInstanceTests * Changed invoke to makeScope Nested makeScopes share same state object Removed earlier named string buffer implementation * Better name for captor get data * Add trace tests to make sure it works too * Fix call into logger settings
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Update rename2 (#478)Adam Izraelevitz
* Added pass name to debug logger * Addresses #459. Rewords transform annotations API. Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. * Added more stylized debugging style * WIP: make pass transform * WIP: All tests pass, need to pull master * Cleaned up PR * Added rename updates to all core transforms * Added more rename tests, and bugfixes * Renaming tracks non-leaf subfields E.g. given: wire x: {a: UInt<1>, b: UInt<1>[2]} Annotating x.b will eventually annotate x_b_0 and x_b_1 * Bugfix instance rename lowering broken * Address review comments * Remove check for seqTransform, UnknownForm too restrictive check
2017-03-17Give better error message if missing emitedcircuitAdam Izraelevitz
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2017-03-06Added more stylized debugging styleAdam Izraelevitz
2017-02-27castrhs shouldn't assume rhs is uint (#467)Angie Wang
* castrhs shouldn't assume rhs is uint * don't cast if types are the same * changed castrhs to catch invalid lhs, rhs type combinations * change error msg
2017-02-23move more general utils out of memutils, mov WIR helpers to WIR.scala and ↵Angie
update uses
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
Also add support for width inference
2017-01-05Fix ScalaDoc complaints; add sbt-site, sbt-ghpages boilerplate.Jim Lawson
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-10-27Wiring (#348)Adam Izraelevitz
Added wiring pass and simple test
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-27remove unnecessary parentheseschick
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25stuff like this mutable.LinkedHashMap needs the mutable prefixchick
2016-09-25implicit functions should specify return typechick
2016-09-25Minor fixes, typo in wordchick
missing declarations in scala doc
2016-09-13Fix a lurking width-inference bug; improve adjacent style (#298)Andrew Waterman
ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)). I noticed this because of #297.
2016-09-13use case object for WVoid, WInvalidDonggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-13remove Utils.{width_BANG, long_BANG}Donggyu Kim
2016-09-13remove Utils.get_typeDonggyu Kim
2016-09-13remove Utils.{mapr, get_name} and fix spacesDonggyu Kim
2016-09-13clean up MemUtilsDonggyu Kim
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
hidden const props not desirable
2016-09-07refactor checksDonggyu Kim
2016-09-07clean up miscsDonggyu Kim
2016-09-07clean up Utils.scalaDonggyu Kim
remove unnecessary functions & change spaces
2016-09-07remove Utils.ONEDonggyu Kim
2016-09-07remove Utils.tpeDonggyu Kim
2016-09-07Utils.scala: remove vars with foldDonggyu Kim
2016-09-06replace flatMap with foldLeft in create_expsDonggyu Kim
internal implementation for flatMap seems to be inefficient
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