| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-01-16 | Added some comments | azidar | |
| 2015-12-06 | Working on generating SimTop, need to figure out how to split the top-level ↵ | jackkoenig | |
| IO between the sim modules. | |||
| 2015-12-04 | Everything is broken, need Translator to work on files without a circuit, ↵ | jackkoenig | |
| need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala | |||
| 2015-10-02 | Merged in Scala implementation of FIRRTL IR, parser, and serialization (ie. ↵ | Jack | |
| AST -> String). Uses ANTLRv4 to generate concrete syntax parser | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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