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Prefix temporary names with underscores so Verilator won't trace them
Use verilator argument "--trace-underscore" if you want to trace these
signals
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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there's a big stack overhead with mappers
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* Corrected names to match current RW port spec
* Added Jack's Namespace on Circuit
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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Replace use of gensym with local namespaces
Delete gensym
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