| Age | Commit message (Collapse) | Author |
|---|
|
Performs DCE by constructing a global dependency graph starting with top-level
outputs, external module ports, and simulation constructs as circuit sinks.
External modules can optionally be eligible for DCE via the
OptimizableExtModuleAnnotation.
Dead code is eliminated across module boundaries. Wires, ports, registers, and
memories are all eligible for removal. Components marked with a
DontTouchAnnotation will be treated as a circuit sink and thus anything that
drives such a marked component will NOT be removed.
This transform preserves deduplication. All instances of a given DefModule are
treated as the same individual module. Thus, while certain instances may have
dead code due to the circumstances of their instantiation in their parent
module, they will still not be removed. To remove such modules, use the
NoDedupAnnotation to prevent deduplication.
|
|
* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
|
|
|
|
|
|
* Added Zero width wires.
Semantics:
- No change to width inference rules, e.g.
a<0> + b<2> = c<3>
- Replace zero width wires with UInt<1>(0) or SInt<1>(0)
- Performs constant prop.
- Redo width/type inference
* Remove errant println
* Moved ZeroWidth after ConvertFixedToSInt
* Added more tests, bugfix match on connect
Also replaced constprop with infertypes for correctness
* Updated to new emitter and test infrastructure
|
|
Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
|
|
|
|
* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory
* A little bit of style cleanup
* A little bit of style cleanup
* Fix the driver, wasn't appending targetDir properly
Add some docs
* test had wrong value now that targetdir is added to annnos
* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line
* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there
* targetDir annotation is targeted to a CircuitName("All")
|
|
|
|
Also run CheckTypes after ExpandWhens
Fixes #330
|
|
Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
|
|
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
|
|
Makes low firrtl more like a netlist, should probably update spec
|
|
* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
|
|
* Create a simple system for executions and command line parameters
New model for tracking parameters and having those parameters
register scopt command to allow the parameters to be set by
command line args.
Create composable forms of the these parameters to allow separate
elements of the chisel3 toolchain to combine these parameters
Create execution return structures that simplify return values
to earlier toolchain elements
* just a little bit of cleanup
* Fixes for Adam's comments on PR
* knuckled under to self-pressure to allow former -i and -o to work
* knuckled under to self-pressure to allow former -i and -o to work
* show defaults for command line args with them
* A couple of fixes from merging latest master
* Implement a log4scala like logging system
This system has the rather remarkable property
that it is possible to turn it on conveniently when
you want it. It also provides for class level granularity
as well as the traditional Error, Warn, Info, Debug
* some style fixes and change infoMode default to append per PR #328
* some style fixes and change infoMode default to append per PR #328
* support -i -o and -X
a couple of indentation and spacing fixes
|
|
* Reorganized memory blackboxing
Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala
* Fixed tests to pass
* Use DefAnnotatedMemory instead of AppendableInfo
* Broke passes up into simpler passes
AnnotateMemMacros ->
(ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
(RenameAnnotatedMemoryPorts, ResolveMemoryReference)
* Fixed to make tests run
* Minor changes from code review
* Removed vim comments and renamed ReplSeqMem
|
|
* WIP: Adding FixedType to Firrtl proper
Got simple example running through width inference
Checks should be ok
Need to look into FixedLiteral more
* Added simple test for fixed types
* Added asFixedPoint to primops
* Added tail case for FixedType
* Added ConvertFixedToSInt.scala
Added pass to MiddleToLowerFirrtl transform
* Replace AsFixedType with AsSInt in fixed removal
* Bugfix: constant from asFixed not deleted
* Added unit test for bulk connect
* Fixed partial connect bug #241
* Fixed missing case for FixedPoint in legalizeConnect
* Add FixedMathSpec that demonstrates some problems with FixedPointMath
* Fixed test and ConvertToSInt to pass.
Negative binary points not easily supported, needs much more time to
implement.
* Refactored checking neg widths
Make checking for negative binary points easier
* Added tests for inferring many FixedType ops
shl, shr, cat, bits, head, tail, setbp, shiftbp
* Handle bpshl, bpshr, bpset in ConvertFixedToSInt
Changed name from shiftbp -> bpshl, bpshr
Change name from setbp -> bpset
Added more tests
* Added set binary point test that fails
* Added simple test for zero binary point
* gitignore fixes for antlr intermediate dir and intellij dir
* removed unused imports
retool the fixed point with zero binary point test
* simplified example of inability to set binary point to zero
* Temporary fix for zero-width binary point
This fix allows for all widths to be zero, but since this is a feature I
am working on next, I'm not going to bother with a more stringent check.
* change version for dsp tools
* Removed extra temporary file
* Fixed merge bug
* Fixed another merge bug
* Removed commented out/unrelated files
* Removed snake case
|
|
* Spec features added: AnalogType and Attach
AnalogType(width: Width):
- Concrete syntax:
wire x: AnalogType<10>
- New groundtype, very restricted in use cases.
- Can only declare ports and wires with Analog type
- Analog types are never equivalent, thus if x and y have Analog
types: x <= y is never legal.
Attach(info: Info, source: Expression, exprs: Seq[Expression]):
- Concrete syntax:
attach x to (y, z)
- New statement
- Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
- Exprs must have an Analog type reference an instance port
- Source and exprs must have identical widths
Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.
* Fixed bug where invalidated ports aren't handled
* Bugfix for VerilogPrep
Intermediate wires for invalidated instance ports were not invalidated
* Bugfix: calling create_exp with name/tpe
Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals
* Addressed donggyukim's style comments
* Reworked pass to only allow analog types in attach
Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)
* Fixup bugs from pulling in new changes from master
* comments for type eqs and small style fixes
|
|
discussed with @azidar
|
|
|
|
Bit selecting a literal resulted in invalid Verilog. Legalize now deals with
this by replacing any bits select of UInt or SInt literals with a new literal
composed of the selected bits. Legalize also is now run after PadWidths because
that pass introduces this issue.
Fixes #170
|
|
|
|
|
|
Fix mem infer
|
|
turned on with '--inferRW <circuit name>'
|
|
ConstProp before width padding causes errors for SIntLiteral
|
|
Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206 and #200.
|
|
|
|
Conflicts:
src/main/scala/firrtl/Compiler.scala
src/main/scala/firrtl/LoweringCompilers.scala
src/main/scala/firrtl/passes/Inline.scala
src/test/scala/firrtlTests/AnnotationTests.scala
src/test/scala/firrtlTests/InlineInstancesTests.scala
|
|
Removed InferWidths after ExpandWhens
|
|
|
|
|
|
trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
|
|
Transforms are new unit of modularity within the compiler.
|
