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path: root/src/main/scala/firrtl/LoweringCompilers.scala
AgeCommit message (Expand)Author
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
2019-02-05Add RemoveValidIf to -X mverilogSchuyler Eldridge
2019-02-05Add "mverilog" Compiler Option, Compiler FixesSchuyler Eldridge
2018-12-20Use IdentityTransform to construct NoneCompilerSchuyler Eldridge
2018-11-27Add "none" compiler (#953)Jack Koenig
2018-11-15Combine cats (#851)Albert Chen
2018-08-29Add SystemVerilogCompiler classSchuyler Eldridge
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
2018-07-20Constant prop add (#849)albertchen-sifive
2018-05-21Fix more problems with zero width things. (#779)grebe
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
2017-12-12Add RemoveWires transformJack Koenig
2017-06-28Promote ConstProp to a transformJack Koenig
2017-06-27Add RemoveReset transform to replace register reset with a MuxJack Koenig
2017-06-12Move CheckCombLoops from passes/ to transforms/Jack Koenig
2017-06-12Change CheckCombLoops to a TransformJack Koenig
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-06Zero width (#402)Adam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
2017-02-22[stevo]: Adams fixStevo Bailey
2017-01-31Blackboxhelper (#418)Chick Markley
2016-12-14Add support for top-level use of MiddleFirrtlCompiler.Jim Lawson
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-04Refactor Compilers and Transformsjackkoenig
2016-11-03Added Legalize to MiddleToLowFirrtlazidar
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
2016-10-25Logger 1 (#338)Chick Markley
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
2016-10-17Add fixed point type (#322)Adam Izraelevitz
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
2016-09-25offload latency pipe generation for memories from VerilogEmitterDonggyu Kim
2016-09-14style fixes for Compiler.scala, LoweringCompiler.scalaDonggyu Kim
2016-09-12Legalize bit select. Run Legalize after PadWidths.Jack
2016-09-07Added ReplaceSubAccesses before RemoveSubAccessesazidar
2016-09-06Added starter code for SMem replacementAngie
2016-08-02Merge pull request #203 from ucb-bar/fix_mem_inferAdam Izraelevitz
2016-08-02make infer readwrite ports optionalDonggyu Kim
2016-07-29remove ConstProp in HighFirrtlToMiddleFirrtlDonggyu Kim
2016-07-28InferWidths now only fixes declaration widthsazidar
2016-07-27infer readwrite ports for backward compatibilityDonggyu Kim
2016-07-27Reworked annotation system. Added tenacity and permissibilityAdam Izraelevitz
2016-07-25Changed InferTypes to update types if UnknownType or has an UnknownWidthazidar
2016-07-21Added a Chirrtl check for undeclared wires, etc.azidar
2016-07-07Re-run constant propagation after pad widthsAndrew Waterman
2016-06-10API Cleanup - ASTJack
2016-05-12Restructured Compiler to use Transforms. Added an InlineInstance pass.Adam Izraelevitz
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