sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-09-25	Spec features added: AnalogType and Attach (#295)	Adam Izraelevitz
	* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25	offload latency pipe generation for memories from VerilogEmitter	Donggyu Kim
	discussed with @azidar
2016-09-14	style fixes for Compiler.scala, LoweringCompiler.scala	Donggyu Kim

2016-09-12	Legalize bit select. Run Legalize after PadWidths.	Jack
	Bit selecting a literal resulted in invalid Verilog. Legalize now deals with this by replacing any bits select of UInt or SInt literals with a new literal composed of the selected bits. Legalize also is now run after PadWidths because that pass introduces this issue. Fixes #170
2016-09-07	Added ReplaceSubAccesses before RemoveSubAccesses	azidar

2016-09-06	Added starter code for SMem replacement	Angie

2016-08-02	Merge pull request #203 from ucb-bar/fix_mem_infer	Adam Izraelevitz
	Fix mem infer
2016-08-02	make infer readwrite ports optional	Donggyu Kim
	turned on with '--inferRW <circuit name>'
2016-07-29	remove ConstProp in HighFirrtlToMiddleFirrtl	Donggyu Kim
	ConstProp before width padding causes errors for SIntLiteral
2016-07-28	InferWidths now only fixes declaration widths	azidar
	Then calls InferTypes to propagate inferred widths to expressions. Required upgrading InferTypes to do simple width propagation. Fixes #206 and #200.
2016-07-27	infer readwrite ports for backward compatibility	Donggyu Kim

2016-07-27	Reworked annotation system. Added tenacity and permissibility	Adam Izraelevitz
	Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-07-25	Changed InferTypes to update types if UnknownType or has an UnknownWidth	azidar
	Removed InferWidths after ExpandWhens
2016-07-21	Added a Chirrtl check for undeclared wires, etc.	azidar

2016-07-07	Re-run constant propagation after pad widths	Andrew Waterman

2016-06-10	API Cleanup - AST	Jack
	trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-12	Restructured Compiler to use Transforms. Added an InlineInstance pass.	Adam Izraelevitz
	Transforms are new unit of modularity within the compiler.