| Age | Commit message (Expand) | Author |
|---|
| 2019-08-13 | Infer reset (#1068) | Jack Koenig |
| 2019-07-08 | Remove some warnings (#1118) | Leway Colin |
| 2019-06-18 | Use scalafix to remove unused import and deprecated procedure syntax (#1074) | Leway Colin |
| 2019-05-24 | Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087) | Jack Koenig |
| 2019-04-25 | Add ShellOption, DeletedWrapper | Schuyler Eldridge |
| 2019-04-25 | Add FirrtlStage, make Driver compatibility layer | Schuyler Eldridge |
| 2019-04-22 | Change Memory Depth to a BigInt (#1075) | Jack Koenig |
| 2019-02-14 | Asynchronous Reset (#1011) | Jack Koenig |
| 2019-02-05 | Add "mverilog" Compiler Option, Compiler Fixes | Schuyler Eldridge |
| 2019-01-23 | Improve Shl codegen; eliminate Shlw WIR node (#994) | Andrew Waterman |
| 2018-11-29 | Replace Mappers with Foreachers in several passes (#954) | Albert Magyar |
| 2018-11-27 | Add foreach as alternative to map (#952) | Adam Izraelevitz |
| 2018-11-27 | Add "none" compiler (#953) | Jack Koenig |
| 2018-11-15 | Combine cats (#851) | Albert Chen |
| 2018-10-12 | Refactor VerilogRename -> RemoveKeywordCollisions | Schuyler Eldridge |
| 2018-08-30 | Emit Verilog Comments (#874) | albertchen-sifive |
| 2018-08-21 | Allow the #delay before random initialization to be overridden | Andrew Waterman |
| 2018-08-10 | allowing overrides to $random (#859) | Deborah Soung |
| 2018-07-26 | Support for load memory annotations in chisel (#833) | Chick Markley |
| 2018-05-29 | Fix pad (#817) | Jack Koenig |
| 2018-05-15 | Replace truncating add and sub with addw/subw (#800) | Jack Koenig |
| 2018-03-27 | Change throwInternalError to use a String instead of Option[String] (#777) | Jack Koenig |
| 2018-03-23 | Make Register Update Flattening a Transform and Delete Dangling Nodes (#692) | Jack Koenig |
| 2018-02-27 | Refactor Annotations (#721) | Jack Koenig |
| 2018-02-22 | Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu... | Adam Izraelevitz |
| 2018-02-16 | Replacematcherror - catch exceptions and convert to internal error. (#424) | Jim Lawson |
| 2018-01-05 | Remove erroneous undef of RANDOMIZE in emitted Verilog | Jack Koenig |
| 2017-12-27 | Removed top preamble (#640) | Adam Izraelevitz |
| 2017-11-08 | Emit source locators as comments in emitted Verilog | Jack Koenig |
| 2017-09-22 | Fix string lit (#663) | Jack Koenig |
| 2017-08-23 | Reorder port and wire assignments in Verilog (#641) | Adam Izraelevitz |
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig |
| 2017-06-12 | Fixes a typo in the verilog `elsif code generation (#603) | Shreesha Srinath |
| 2017-05-30 | Change base of randomization values to _RAND instead of _GEN | Jack Koenig |
| 2017-05-30 | Add some comments to `endif | Jack Koenig |
| 2017-05-11 | Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586) | Jim Lawson |
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz |
| 2017-03-06 | After merge, fixed added transforms | Adam Izraelevitz |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2017-02-26 | Align types and names of ports in emitted Verilog (#463) | Jack Koenig |
| 2017-02-23 | Fix warning from Cadence Incisive | Scott Johnson |
| 2017-02-14 | Add println/throwInternalError to Emitter | Adam Izraelevitz |
| 2017-02-13 | Emit memories larger than 512 MB with a sparse annotation (#438) | Colin Schmidt |
| 2017-02-07 | Rework Attach to work on arbitrary Analog hierarchies (#415) | Jack Koenig |
| 2017-01-19 | Verilog rem fix (#404) | grebe |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-31 | Fixed Verilog emission of andr, orr, and xorr (#357) | Adam Izraelevitz |
| 2016-10-26 | Add RawString ExtModule parameter support | jackkoenig |
