sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2020-08-14	All of src/ formatted with scalafmt	chick
2020-08-15	experimental SMTLib and btor2 emitter (#1826)	Kevin Laeufer
2020-08-11	File Serialization of Annotations (#1277)	Schuyler Eldridge
2020-07-30	ir: use Serializer.serialize where possible (#1809)	Kevin Laeufer
2020-07-29	[2.13] fix legacy procedure syntax	Kevin Laeufer
2020-07-29	[2.13] EmissionOptionMap now uses a HashMap instead of extending it	Kevin Laeufer
2020-07-29	[2.13] replace `= Unit` with `= ()`	Kevin Laeufer
2020-07-29	[2.13] convert toSeq and toMap where necessary to compile	Kevin Laeufer
2020-07-25	Integrate new transforms with firrtl.stage.Forms (#1754)	Schuyler Eldridge
2020-07-24	Fix sign extension issue in Emitter (#1785)	Albert Chen
2020-07-23	Update negative literal emission (#1782)	Albert Chen
2020-07-17	Propagate source locators to register update always blocks (#1743)	Jack Koenig
2020-07-15	ir: store FileInfo string in escaped format (#1690)	Kevin Laeufer
2020-07-07	verification: emit mesage as Verilog comment (#1712)	Kevin Laeufer
2020-06-26	Enable ConvertAsserts in default Verilog compiler	Albert Magyar
2020-06-23	Basic model checking API (#1653)	Tom Alcorn
2020-06-22	Support Memory Initialization for Simulation and FPGA Flows (#1645)	Kevin Laeufer
2020-06-22	recore of Attributes (#1643)	Jiuyang Liu
2020-05-26	[API change] Absorb repetitive WIR nodes into IR	Albert Magyar
2020-05-14	Move Reg/Mem initializations to end of module (#1613)	Deborah Soung
2020-05-13	consolidated wire+assign to just wire, with expression inlined (#1600)	Murali Vijayaraghavan
2020-05-05	before/after initial block macros (#1550)	Deborah Soung
2020-05-04	Add LegalizeAndReductionsTransform	Jack Koenig
2020-05-01	Emitter: guard _RAND_* declarations with ifdef (#1548)	Albert Chen
2020-04-22	s/dependents/optionalPrerequisiteOf/	Schuyler Eldridge
2020-04-22	Mixin DependencyAPIMigration to all Transforms	Schuyler Eldridge
2020-04-13	Check EmitAnnotation class before emitting	Schuyler Eldridge
2020-04-13	move asyncInitials inside initial block RANDOMIZE ifdef (#1510)	John Ingalls
2020-03-26	Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)	Chick Markley
2020-03-12	Add Support for FPGA Bitstream Preset-registers (#1050)	John's Brew
2020-03-11	Migrate to DependencyAPI	Schuyler Eldridge
2020-03-04	Revert "Verilog emitter transform InlineNots (#1270)"	Albert Magyar
2020-02-12	Fixing lint error: x + -1 (#1374)	Adam Izraelevitz
2020-02-06	Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)	Albert Magyar
2020-01-21	Refactoring checkCatArgumentLegality (#1317)	Derek Pappas
2020-01-15	Verilog emitter transform InlineBitExtractions (#1296)	John Ingalls
2020-01-07	Fix literals cast to Clocks in Print and Stop	Jack Koenig
2020-01-07	Remove unnecessary $signed casts for PrimOps in Verilog Emitter	Jack Koenig
2020-01-06	Verilog emitter transform InlineNots (#1270)	John Ingalls
2020-01-06	Make EmittedAnnotation Unserializable (#1288)	Schuyler Eldridge
2019-10-31	Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS	Jack Koenig
2019-10-22	Emit Verilog "else if" in register updates	Schuyler Eldridge
2019-09-16	Rename gender to flow	Schuyler Eldridge
2019-08-13	Infer reset (#1068)	Jack Koenig
2019-07-08	Remove some warnings (#1118)	Leway Colin
2019-06-18	Use scalafix to remove unused import and deprecated procedure syntax (#1074)	Leway Colin
2019-05-24	Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)	Jack Koenig
2019-04-25	Add ShellOption, DeletedWrapper	Schuyler Eldridge
2019-04-25	Add FirrtlStage, make Driver compatibility layer	Schuyler Eldridge
2019-04-22	Change Memory Depth to a BigInt (#1075)	Jack Koenig