sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-04-26	Make sure nested expressions don't make it to the Emitter	Andrew Waterman
2016-04-22	Refactor LowerTypes	jackkoenig
2016-04-20	Change RemoveCHIRRTL to define port clocks at CHIRRTL port definition	jackkoenig
2016-04-16	Add Namespace for thread-safe creation of names and temporary names	jackkoenig
2016-04-15	Fix Verilog emission for Modelsim compliation	Andrew Waterman
2016-04-07	Add primitive dead code elimination pass	Andrew Waterman
2016-04-06	Merge pull request #102 from ucb-bar/propagate-mem-port-types	Adam Izraelevitz
2016-04-04	Wrapped delay in ifndef verilator, as it is not supported by verilator	Adam Izraelevitz
2016-04-01	Propagate memory port types in Emitter	Andrew Waterman
2016-03-18	Add guard to emission of simulation constructs	jackkoenig
2016-03-15	Change non-reentrant VerilogEmitter from object to class	Jack
2016-03-15	Revamp string literal handling	jackkoenig
2016-03-10	Add support for right shift by amount larger than argument width	jackkoenig
2016-03-01	Move mapper functions to implicit methods on IR vertices.	jackkoenig
2016-02-25	Separate serialize functions into separate file	jackkoenig
2016-02-25	Remove FlagUtils and related unused debug printing	jackkoenig
2016-02-24	Fixed printf bugs in scala and stanza versions. Required special casing print...	Adam Izraelevitz
2016-02-24	Quick fix for printf in the emitted Verilog	Kamyar Mohajerani
2016-02-09	Added license to FIRRTL files	azidar
2016-02-09	CHIRRTL passes work, parser is updated	azidar
2016-02-09	Added chirrtl passes, need to update parser	azidar
2016-02-09	More bug fixes	azidar
2016-02-09	Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ...	azidar
2016-02-09	Restructure passes to be new subpackage with more modular design, add new str...	Jack