sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-09-25	offload latency pipe generation for memories from VerilogEmitter	Donggyu Kim
2016-09-25	more readable verilog generation for register updates	Donggyu Kim
2016-09-25	stuff like this mutable.LinkedHashMap needs the mutable prefix	chick
2016-09-25	remove unnecessary blocks	chick
2016-09-25	convert all occurencess of BigInt == Int to BigInt == BigInt	chick
2016-09-25	Use empty-parens as appropriate for f: => Unit calls	chick
2016-09-23	Use parens on Unit methods	chick
2016-09-23	use .isEmpty, .nonEmpty, isDefined	chick
2016-09-23	use .head instead of (0)	chick
2016-09-16	fill empty module body with "begin end" (#305)	Yunsup Lee
2016-09-13	remove VIndent	Donggyu Kim
2016-09-13	use case object for Kind	Donggyu Kim
2016-09-13	remove Utils.{width_BANG, long_BANG}	Donggyu Kim
2016-09-13	remove Utils.get_type	Donggyu Kim
2016-09-13	use MemPortUtils.memType for DefMemory	Donggyu Kim
2016-09-12	Rework map functions as class methods	jackkoenig
2016-09-08	remove Utils.{AND, OR, NOT, EQV}	Donggyu Kim
2016-09-07	clean up Emitter.scala (#275)	Donggyu
2016-09-07	clean up Utils.scala	Donggyu Kim
2016-09-07	remove Utils.tpe	Donggyu Kim
2016-09-05	Change null statement to empty begin end (#264)	Colin Schmidt
2016-08-25	emit wires instead of registers for invalid randomization	Howard Mao
2016-08-25	Finer grained control over randomization	Howard Mao
2016-08-18	emit correct enable signals for memories (#242)	Donggyu
2016-08-17	Change RW port names (#236)	Angie Wang
2016-08-02	Change serialize to abstract method on FirrtlNode	Jack Koenig
2016-07-21	Indentation support for the ANTLR parser (as discussed in #192) (#194)	Kamyar Mohajerani
2016-07-07	Guard register randomization with RANDOMIZE, rather than SYNTHESIS	Andrew Waterman
2016-07-06	Emit correct Verilog for SIntLiteral	Andrew Waterman
2016-07-06	Only assign garbage to Mem reads for non-power-of-2 depths	Andrew Waterman
2016-07-06	Avoid width warnings on Mem garbage assignment	Andrew Waterman
2016-07-06	Rely on $fatal vs. $finish, rather than stderr, for stop codes	Andrew Waterman
2016-06-27	Optionally guard stop with `STOP_COND macro	Andrew Waterman
2016-06-23	Emit more useful code for stop	Andrew Waterman
2016-06-10	API Cleanup - AST	Jack
2016-06-10	API Cleanup - PrimOp & PrimOps	Jack
2016-06-10	API Cleanup - Expression	Jack
2016-06-10	API Cleanup - Statement	Jack
2016-06-10	API Cleanup - Width	Jack
2016-06-10	API Cleanup - Type	Jack
2016-06-10	API Cleanup - Port & Direction	Jack
2016-06-10	API Cleanup - Module	Jack
2016-06-10	Avoid exponential growth in reg code emission	Andrew Waterman
2016-06-10	Fix Verilog codegen for reg	Andrew Waterman
2016-06-09	Initializes register addresses. (#189)	Adam Izraelevitz
2016-06-06	Guard mem read ports with random data if read addr is out of range	jackkoenig
2016-05-24	Remove nested AND in creation of readwrite ports for mems.	jackkoenig
2016-05-10	Added pad widths to eliminate all implicit width extending	Adam Izraelevitz
2016-05-10	Fixed emission of memory ports to all be in the same always @ clock.	Adam Izraelevitz
2016-05-03	Remove line in Verilog Emitter erroneously printing ); before module def	jackkoenig