sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2020-03-26	Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)	Chick Markley
2020-03-12	Add Support for FPGA Bitstream Preset-registers (#1050)	John's Brew
2020-03-11	Migrate to DependencyAPI	Schuyler Eldridge
2020-03-04	Revert "Verilog emitter transform InlineNots (#1270)"	Albert Magyar
2020-02-12	Fixing lint error: x + -1 (#1374)	Adam Izraelevitz
2020-02-06	Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)	Albert Magyar
2020-01-21	Refactoring checkCatArgumentLegality (#1317)	Derek Pappas
2020-01-15	Verilog emitter transform InlineBitExtractions (#1296)	John Ingalls
2020-01-07	Fix literals cast to Clocks in Print and Stop	Jack Koenig
2020-01-07	Remove unnecessary $signed casts for PrimOps in Verilog Emitter	Jack Koenig
2020-01-06	Verilog emitter transform InlineNots (#1270)	John Ingalls
2020-01-06	Make EmittedAnnotation Unserializable (#1288)	Schuyler Eldridge
2019-10-31	Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS	Jack Koenig
2019-10-22	Emit Verilog "else if" in register updates	Schuyler Eldridge
2019-09-16	Rename gender to flow	Schuyler Eldridge
2019-08-13	Infer reset (#1068)	Jack Koenig
2019-07-08	Remove some warnings (#1118)	Leway Colin
2019-06-18	Use scalafix to remove unused import and deprecated procedure syntax (#1074)	Leway Colin
2019-05-24	Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)	Jack Koenig
2019-04-25	Add ShellOption, DeletedWrapper	Schuyler Eldridge
2019-04-25	Add FirrtlStage, make Driver compatibility layer	Schuyler Eldridge
2019-04-22	Change Memory Depth to a BigInt (#1075)	Jack Koenig
2019-02-14	Asynchronous Reset (#1011)	Jack Koenig
2019-02-05	Add "mverilog" Compiler Option, Compiler Fixes	Schuyler Eldridge
2019-01-23	Improve Shl codegen; eliminate Shlw WIR node (#994)	Andrew Waterman
2018-11-29	Replace Mappers with Foreachers in several passes (#954)	Albert Magyar
2018-11-27	Add foreach as alternative to map (#952)	Adam Izraelevitz
2018-11-27	Add "none" compiler (#953)	Jack Koenig
2018-11-15	Combine cats (#851)	Albert Chen
2018-10-12	Refactor VerilogRename -> RemoveKeywordCollisions	Schuyler Eldridge
2018-08-30	Emit Verilog Comments (#874)	albertchen-sifive
2018-08-21	Allow the #delay before random initialization to be overridden	Andrew Waterman
2018-08-10	allowing overrides to $random (#859)	Deborah Soung
2018-07-26	Support for load memory annotations in chisel (#833)	Chick Markley
2018-05-29	Fix pad (#817)	Jack Koenig
2018-05-15	Replace truncating add and sub with addw/subw (#800)	Jack Koenig
2018-03-27	Change throwInternalError to use a String instead of Option[String] (#777)	Jack Koenig
2018-03-23	Make Register Update Flattening a Transform and Delete Dangling Nodes (#692)	Jack Koenig
2018-02-27	Refactor Annotations (#721)	Jack Koenig
2018-02-22	Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...	Adam Izraelevitz
2018-02-16	Replacematcherror - catch exceptions and convert to internal error. (#424)	Jim Lawson
2018-01-05	Remove erroneous undef of RANDOMIZE in emitted Verilog	Jack Koenig
2017-12-27	Removed top preamble (#640)	Adam Izraelevitz
2017-11-08	Emit source locators as comments in emitted Verilog	Jack Koenig
2017-09-22	Fix string lit (#663)	Jack Koenig
2017-08-23	Reorder port and wire assignments in Verilog (#641)	Adam Izraelevitz
2017-06-27	Emitting reg update mux tree, only walk netlist for wires and nodes	Jack Koenig
2017-06-12	Fixes a typo in the verilog `elsif code generation (#603)	Shreesha Srinath
2017-05-30	Change base of randomization values to _RAND instead of _GEN	Jack Koenig
2017-05-30	Add some comments to `endif	Jack Koenig