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path: root/src/main/scala/firrtl/Emitter.scala
AgeCommit message (Expand)Author
2016-09-13remove VIndentDonggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-13remove Utils.{width_BANG, long_BANG}Donggyu Kim
2016-09-13remove Utils.get_typeDonggyu Kim
2016-09-13use MemPortUtils.memType for DefMemoryDonggyu Kim
2016-09-12Rework map functions as class methodsjackkoenig
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
2016-09-07clean up Emitter.scala (#275)Donggyu
2016-09-07clean up Utils.scalaDonggyu Kim
2016-09-07remove Utils.tpeDonggyu Kim
2016-09-05Change null statement to empty begin end (#264)Colin Schmidt
2016-08-25emit wires instead of registers for invalid randomizationHoward Mao
2016-08-25Finer grained control over randomizationHoward Mao
2016-08-18emit correct enable signals for memories (#242)Donggyu
2016-08-17Change RW port names (#236)Angie Wang
2016-08-02Change serialize to abstract method on FirrtlNodeJack Koenig
2016-07-21Indentation support for the ANTLR parser (as discussed in #192) (#194)Kamyar Mohajerani
2016-07-07Guard register randomization with RANDOMIZE, rather than SYNTHESISAndrew Waterman
2016-07-06Emit correct Verilog for SIntLiteralAndrew Waterman
2016-07-06Only assign garbage to Mem reads for non-power-of-2 depthsAndrew Waterman
2016-07-06Avoid width warnings on Mem garbage assignmentAndrew Waterman
2016-07-06Rely on $fatal vs. $finish, rather than stderr, for stop codesAndrew Waterman
2016-06-27Optionally guard stop with `STOP_COND macroAndrew Waterman
2016-06-23Emit more useful code for stopAndrew Waterman
2016-06-10API Cleanup - ASTJack
2016-06-10API Cleanup - PrimOp & PrimOpsJack
2016-06-10API Cleanup - ExpressionJack
2016-06-10API Cleanup - StatementJack
2016-06-10API Cleanup - WidthJack
2016-06-10API Cleanup - TypeJack
2016-06-10API Cleanup - Port & DirectionJack
2016-06-10API Cleanup - ModuleJack
2016-06-10Avoid exponential growth in reg code emissionAndrew Waterman
2016-06-10Fix Verilog codegen for regAndrew Waterman
2016-06-09Initializes register addresses. (#189)Adam Izraelevitz
2016-06-06Guard mem read ports with random data if read addr is out of rangejackkoenig
2016-05-24Remove nested AND in creation of readwrite ports for mems.jackkoenig
2016-05-10Added pad widths to eliminate all implicit width extendingAdam Izraelevitz
2016-05-10Fixed emission of memory ports to all be in the same always @ clock.Adam Izraelevitz
2016-05-03Remove line in Verilog Emitter erroneously printing ); before module defjackkoenig
2016-04-26Make sure nested expressions don't make it to the EmitterAndrew Waterman
2016-04-22Refactor LowerTypesjackkoenig
2016-04-20Change RemoveCHIRRTL to define port clocks at CHIRRTL port definitionjackkoenig
2016-04-16Add Namespace for thread-safe creation of names and temporary namesjackkoenig
2016-04-15Fix Verilog emission for Modelsim compliationAndrew Waterman
2016-04-07Add primitive dead code elimination passAndrew Waterman
2016-04-06Merge pull request #102 from ucb-bar/propagate-mem-port-typesAdam Izraelevitz
2016-04-04Wrapped delay in ifndef verilator, as it is not supported by verilatorAdam Izraelevitz
2016-04-01Propagate memory port types in EmitterAndrew Waterman
2016-03-18Add guard to emission of simulation constructsjackkoenig
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