| Age | Commit message (Expand) | Author |
|---|
| 2017-11-08 | Emit source locators as comments in emitted Verilog | Jack Koenig |
| 2017-09-22 | Fix string lit (#663) | Jack Koenig |
| 2017-08-23 | Reorder port and wire assignments in Verilog (#641) | Adam Izraelevitz |
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig |
| 2017-06-12 | Fixes a typo in the verilog `elsif code generation (#603) | Shreesha Srinath |
| 2017-05-30 | Change base of randomization values to _RAND instead of _GEN | Jack Koenig |
| 2017-05-30 | Add some comments to `endif | Jack Koenig |
| 2017-05-11 | Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586) | Jim Lawson |
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz |
| 2017-03-06 | After merge, fixed added transforms | Adam Izraelevitz |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2017-02-26 | Align types and names of ports in emitted Verilog (#463) | Jack Koenig |
| 2017-02-23 | Fix warning from Cadence Incisive | Scott Johnson |
| 2017-02-14 | Add println/throwInternalError to Emitter | Adam Izraelevitz |
| 2017-02-13 | Emit memories larger than 512 MB with a sparse annotation (#438) | Colin Schmidt |
| 2017-02-07 | Rework Attach to work on arbitrary Analog hierarchies (#415) | Jack Koenig |
| 2017-01-19 | Verilog rem fix (#404) | grebe |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-31 | Fixed Verilog emission of andr, orr, and xorr (#357) | Adam Izraelevitz |
| 2016-10-26 | Add RawString ExtModule parameter support | jackkoenig |
| 2016-10-26 | Add Support for Parameterized ExtModules and Name Override | jackkoenig |
| 2016-10-11 | Scala style cleanup take 5 (#324) | Chick Markley |
| 2016-09-27 | remove unnecessary parentheses | chick |
| 2016-09-25 | Spec features added: AnalogType and Attach (#295) | Adam Izraelevitz |
| 2016-09-25 | offload latency pipe generation for memories from VerilogEmitter | Donggyu Kim |
| 2016-09-25 | more readable verilog generation for register updates | Donggyu Kim |
| 2016-09-25 | stuff like this mutable.LinkedHashMap needs the mutable prefix | chick |
| 2016-09-25 | remove unnecessary blocks | chick |
| 2016-09-25 | convert all occurencess of BigInt == Int to BigInt == BigInt | chick |
| 2016-09-25 | Use empty-parens as appropriate for f: => Unit calls | chick |
| 2016-09-23 | Use parens on Unit methods | chick |
| 2016-09-23 | use .isEmpty, .nonEmpty, isDefined | chick |
| 2016-09-23 | use .head instead of (0) | chick |
| 2016-09-16 | fill empty module body with "begin end" (#305) | Yunsup Lee |
| 2016-09-13 | remove VIndent | Donggyu Kim |
| 2016-09-13 | use case object for Kind | Donggyu Kim |
| 2016-09-13 | remove Utils.{width_BANG, long_BANG} | Donggyu Kim |
| 2016-09-13 | remove Utils.get_type | Donggyu Kim |
| 2016-09-13 | use MemPortUtils.memType for DefMemory | Donggyu Kim |
| 2016-09-12 | Rework map functions as class methods | jackkoenig |
| 2016-09-08 | remove Utils.{AND, OR, NOT, EQV} | Donggyu Kim |
| 2016-09-07 | clean up Emitter.scala (#275) | Donggyu |
| 2016-09-07 | clean up Utils.scala | Donggyu Kim |
| 2016-09-07 | remove Utils.tpe | Donggyu Kim |
| 2016-09-05 | Change null statement to empty begin end (#264) | Colin Schmidt |
| 2016-08-25 | emit wires instead of registers for invalid randomization | Howard Mao |
| 2016-08-25 | Finer grained control over randomization | Howard Mao |
| 2016-08-18 | emit correct enable signals for memories (#242) | Donggyu |
