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* Upgrade Logging facility
Make thread-safe
Make logging by package name work
Use caching of class names to level for performance
Make some tests to show this working
* quick fix for dynamic logging variable
* A number of changes based on Adam's suggestions
Default LoggerState
But there is an invoke method now to handle threading issues. This should be propagated to other
projects Driver.execute methods
* Add built-in support for string capture of Logging
* Usability fixes for logging stuff. Settings made to the logger prior to execute/invoke will be passed along if possible.
* A couple style fixes
Comment and privatize Logger state
* Name and save string buffers used for logging
* Fix default logging state setting
Fix logging test, did not have change to command argument
* comment out logging in InlineInstanceTests
* Changed invoke to makeScope
Nested makeScopes share same state object
Removed earlier named string buffer implementation
* Better name for captor get data
* Add trace tests to make sure it works too
* Fix call into logger settings
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Now you should be able to copy paste the example code :)
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Also add GlobalCircuitAnnotation for creating similar annotations
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Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
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* fixed up impementation of deleteDirectoryHierarchy
Added a few more tests
* Round 2 of moving verilog to target dir
Only create .f file if some files have been moved
Some small style fixes in Driver
Restored lost functionality to add -f argument in verilogToCpp
Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
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* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory
* A little bit of style cleanup
* A little bit of style cleanup
* Fix the driver, wasn't appending targetDir properly
Add some docs
* test had wrong value now that targetdir is added to annnos
* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line
* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there
* targetDir annotation is targeted to a CircuitName("All")
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* Fixes for Annotation serialized/deserialize
Made serializer agree with deserializer on text representation
Re-ordered serializations of Named subclasses to be C or C.m or C.m.c where C=circuit, m=module, c=component
Note: component may contain dots
Added serialize deserialize tests to AnnotationSpec
Did some style cleanup on AnnotationSpec
Added explicit return tupe on SimpleTransformSpec#execute
* Make explicit Util.error
remove commented code
* Make Annotation#serialize a nicer format
fix import there and remove new on case class
* In firrtl Driver.execute use annotations passed in through optionsManager#firrtlOptions if nonEmpty
otherwise read the annotations in from an annotations file
Add new option to override this behavior, --force-append-anno-file will append annotations in file
to any that are passed in
A few other style fixes to Driver: remove new with case classes. don't use match when if(boolean) will do
* Added tests of malformed component and circuit names
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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* Create a simple system for executions and command line parameters
New model for tracking parameters and having those parameters
register scopt command to allow the parameters to be set by
command line args.
Create composable forms of the these parameters to allow separate
elements of the chisel3 toolchain to combine these parameters
Create execution return structures that simplify return values
to earlier toolchain elements
* just a little bit of cleanup
* Fixes for Adam's comments on PR
* knuckled under to self-pressure to allow former -i and -o to work
* knuckled under to self-pressure to allow former -i and -o to work
* show defaults for command line args with them
* A couple of fixes from merging latest master
* Implement a log4scala like logging system
This system has the rather remarkable property
that it is possible to turn it on conveniently when
you want it. It also provides for class level granularity
as well as the traditional Error, Warn, Info, Debug
* some style fixes and change infoMode default to append per PR #328
* some style fixes and change infoMode default to append per PR #328
* support -i -o and -X
a couple of indentation and spacing fixes
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firrtl compiler
Fixes colin's problem with repl-seq-mem not creating a conf file.
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Create a simple system for executions and command line parameters
New model for tracking parameters and having those parameters
register scopt command to allow the parameters to be set by
command line args.
Create composable forms of the these parameters to allow separate
elements of the chisel3 toolchain to combine these parameters
Create execution return structures that simplify return values
to earlier toolchain elements
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* Reorganized memory blackboxing
Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala
* Fixed tests to pass
* Use DefAnnotatedMemory instead of AppendableInfo
* Broke passes up into simpler passes
AnnotateMemMacros ->
(ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
(RenameAnnotatedMemoryPorts, ResolveMemoryReference)
* Fixed to make tests run
* Minor changes from code review
* Removed vim comments and renamed ReplSeqMem
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this makes it much easier to see where something
went wrong during compilation if the lines have
no info initially or its on internal nodes
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example 1 s"${x}"
example 2 case blah => { ??? }
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* Also started separate pass for annotating valid memory
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Now prints usage when given incorrect arguments
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Creating the output file preemptively screws up make, as on
subsequent executions of make, it thinks the task succeeded.
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turned on with '--inferRW <circuit name>'
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Conflicts:
src/main/scala/firrtl/Compiler.scala
src/main/scala/firrtl/LoweringCompilers.scala
src/main/scala/firrtl/passes/Inline.scala
src/test/scala/firrtlTests/AnnotationTests.scala
src/test/scala/firrtlTests/InlineInstancesTests.scala
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Transforms are new unit of modularity within the compiler.
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use StringWriters without the Compiler closing it)
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structures Compiler and Emitter, deprecate old Passes object, update Driver to use new constructs
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flying around everywhere
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map.
Also rewrite main so stanza and scala passes can be intermixed.
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ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice
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IO between the sim modules.
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