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* Fixes for Annotation serialized/deserialize
Made serializer agree with deserializer on text representation
Re-ordered serializations of Named subclasses to be C or C.m or C.m.c where C=circuit, m=module, c=component
Note: component may contain dots
Added serialize deserialize tests to AnnotationSpec
Did some style cleanup on AnnotationSpec
Added explicit return tupe on SimpleTransformSpec#execute
* Make explicit Util.error
remove commented code
* Make Annotation#serialize a nicer format
fix import there and remove new on case class
* In firrtl Driver.execute use annotations passed in through optionsManager#firrtlOptions if nonEmpty
otherwise read the annotations in from an annotations file
Add new option to override this behavior, --force-append-anno-file will append annotations in file
to any that are passed in
A few other style fixes to Driver: remove new with case classes. don't use match when if(boolean) will do
* Added tests of malformed component and circuit names
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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Conflicts:
src/main/scala/firrtl/Compiler.scala
src/main/scala/firrtl/LoweringCompilers.scala
src/main/scala/firrtl/passes/Inline.scala
src/test/scala/firrtlTests/AnnotationTests.scala
src/test/scala/firrtlTests/InlineInstancesTests.scala
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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Transforms are new unit of modularity within the compiler.
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RemoveValidIf, SplitExpressions, and PadWidths
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Also add pass to Verilog Compiler list of passes
This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.
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This gives more expressions to eliminate
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use StringWriters without the Compiler closing it)
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rocketchip
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structures Compiler and Emitter, deprecate old Passes object, update Driver to use new constructs
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