| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-11-13 | Add spec for Analog type and attach statement (#1222) | Albert Magyar | |
| * Add spec for Analog type and attach statement * Describe role of attaches in partial connection algorithm * Change references that describe ground types where appropriate * Closes #1194 * Fix typo | |||
| 2019-09-30 | Define read-write collison for independently clocked mem ports (#1188) | Albert Magyar | |
| * Define read-write collison for independently clocked mem ports * Included definition of initiating write/read operation | |||
| 2019-09-16 | Update Spec from Gender to Flow | Schuyler Eldridge | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2019-08-07 | Check mems for legal latencies; ban zero write latency. (#1147) | Albert Magyar | |
| * Check mems for legal latencies; ban zero write latency. * Trigger | |||
| 2019-07-30 | Make write-under-write section for mems in spec (#1140) | Albert Magyar | |
| 2019-06-03 | spec: mixed-input arguments for prim ops are no longer allowed (#1085) | Kevin Laeufer | |
| This updates the spec to refelect the changes made in #587. It also fixes issue #968. | |||
| 2019-03-25 | Correct a typo in spec.tex (#1063) | Felix Yan | |
| 2019-01-31 | Add MidFIRRTL spec (#1003) | Albert Magyar | |
| 2018-09-27 | Number all code examples & add specification build to Makefile (#894) | Ben Marshall | |
| * Merge makefile changes from dev/specification-fixes - New top level makefile target: `specification` - Builds the specification document. * Number all code examples. This is more a change of convenience than anything. Referring to syntax examples is much easier when they are numbered! This commit is in the context of freechipsproject/firrtl#890 - Updating examples and syntax specification is made easier if they are numbered. - Change `verbatim` environments to `lstlisting` - Add very basic keyword highlighting. - Rebuild specification PDF. On branch dev/number-code-examples Changes to be committed: modified: spec/spec.pdf modified: spec/spec.tex | |||
| 2018-06-11 | Fix some typos in leftovers.txt (#822) | Felix Yan | |
| 2018-03-20 | Correct extmodule example in spec (#768) | Albert Magyar | |
| 2018-02-16 | Update spec for rhs | Schuyler Eldridge | |
| Fixes #450 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2017-12-24 | Spec erroneously says mod instead of rem. | Paul Rigge | |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz | |
| SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+). | |||
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig | |
| Replace with more sensible comment to see LICENSE rather than including the whole license in every file | |||
| 2016-11-03 | Updated future release with stricter low firrtl | azidar | |
| 2016-09-22 | Fixed width inference for add, sub (#312) | Adam Izraelevitz | |
| Fixes #308 Fixes #193 | |||
| 2016-08-17 | Change RW port names (#236) | Angie Wang | |
| * Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch. | |||
| 2016-08-16 | Spec bugfix: update concrete reg syntax example (#233) | Adam Izraelevitz | |
| Also added clock to reg's abstract syntax | |||
| 2016-07-27 | Merge pull request #205 from ucb-bar/add-future-release | Adam Izraelevitz | |
| Added future-release.txt | |||
| 2016-07-27 | Added future-release.txt | azidar | |
| Keeps track of proposed changes to add to the next version of the Firrtl spec. | |||
| 2016-07-27 | Fixed reg concrete syntax. #197. | azidar | |
| 2016-05-23 | Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ↵ | azidar | |
| just be a string. Removed symbols from identifiers except '_' | |||
| 2016-02-23 | Updated pdf | azidar | |
| 2016-02-09 | Added license to FIRRTL files | azidar | |
| 2016-02-09 | Added changes that addressed feedback, spec ready for release | azidar | |
| 2016-01-28 | Changed rmode to wmode | azidar | |
| 2016-01-28 | Changed mod to rem | azidar | |
| 2016-01-28 | Updated todo list | azidar | |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar | |
| 2016-01-27 | Reworked readwriter types | azidar | |
| 2016-01-25 | Added verilog rename pass | azidar | |
| 2016-01-25 | Removed random println | azidar | |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar | |
| 2016-01-23 | Added inference to mports | azidar | |
| 2016-01-22 | Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-mem | azidar | |
| Conflicts: spec/spec.pdf | |||
| 2016-01-22 | Added pdf | azidar | |
| 2016-01-22 | Added a word | azidar | |
| 2016-01-22 | Added funding number, as well as additional acknowledgements | azidar | |
| 2016-01-22 | Finished version 0.2.0. Included leftovers for future user manual. | azidar | |
| 2016-01-21 | First cut, some unfinished sections but readable | azidar | |
| 2016-01-20 | WIP, almost finished with expressions. Removed poison, add is invalid and ↵ | azidar | |
| validif() | |||
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar | |
| 2016-01-20 | WIP: finished partial connect | azidar | |
| 2016-01-19 | WIP: Writing new spec. | azidar | |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵ | azidar | |
| to be specified with write and rdwr mports | |||
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar | |
| 2016-01-16 | WIP adding chirrtl | azidar | |
| 2016-01-16 | WIP | azidar | |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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