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2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
Fixes #308 Fixes #193
2016-08-17Change RW port names (#236)Angie Wang
* Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch.
2016-08-16Spec bugfix: update concrete reg syntax example (#233)Adam Izraelevitz
Also added clock to reg's abstract syntax
2016-07-27Fixed reg concrete syntax. #197.azidar
2016-05-23Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ↵azidar
just be a string. Removed symbols from identifiers except '_'
2016-02-23Updated pdfazidar
2016-02-09Added license to FIRRTL filesazidar
2016-02-09Added changes that addressed feedback, spec ready for releaseazidar
2016-01-28Changed rmode to wmodeazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated todo listazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-25Added verilog rename passazidar
2016-01-25Removed random printlnazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-23Added inference to mportsazidar
2016-01-22Added a wordazidar
2016-01-22Added funding number, as well as additional acknowledgementsazidar
2016-01-22Finished version 0.2.0. Included leftovers for future user manual.azidar
2016-01-21First cut, some unfinished sections but readableazidar
2016-01-20WIP, almost finished with expressions. Removed poison, add is invalid and ↵azidar
validif()
2016-01-20WIP: finished partial connectazidar
2016-01-19WIP: Writing new spec.azidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵azidar
to be specified with write and rdwr mports
2016-01-16WIPazidar
2015-10-06Updated spec to mention sign extending widths of operand inputsazidar
2015-09-24Added poison node to specazidar
2015-09-01Added cases of undefined behavior for cmem and smemazidar
2015-08-31Changed Bulk to Partial, <> to <-, and := to <=azidar
2015-08-31Updated specazidar
2015-07-23Updated specazidar
2015-07-22Minor updates to specazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-06-30Updated TODO. Ran spelling/grammar check on specazidar
2015-06-29Fixed minor typos. As of now, the finished version for internal feedback.azidar
2015-06-26Changed clock from port kind to typeazidar
2015-06-26Finished draft of Version 0.1.3. Ready for comments.azidar
2015-06-23More updates to specazidar
2015-06-22Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessorsazidar
2015-06-12Added more changes to specazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-04-15Finished flo backend. Restructured todo listazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
2015-03-10Finished resolve gendersazidar
2015-03-04Finished infer-types passazidar
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