| Age | Commit message (Expand) | Author |
|---|
| 2019-11-13 | Add spec for Analog type and attach statement (#1222) | Albert Magyar |
| 2019-09-30 | Define read-write collison for independently clocked mem ports (#1188) | Albert Magyar |
| 2019-09-16 | Update Spec from Gender to Flow | Schuyler Eldridge |
| 2019-08-07 | Check mems for legal latencies; ban zero write latency. (#1147) | Albert Magyar |
| 2019-07-30 | Make write-under-write section for mems in spec (#1140) | Albert Magyar |
| 2019-06-03 | spec: mixed-input arguments for prim ops are no longer allowed (#1085) | Kevin Laeufer |
| 2019-03-25 | Correct a typo in spec.tex (#1063) | Felix Yan |
| 2019-01-31 | Add MidFIRRTL spec (#1003) | Albert Magyar |
| 2018-09-27 | Number all code examples & add specification build to Makefile (#894) | Ben Marshall |
| 2018-03-20 | Correct extmodule example in spec (#768) | Albert Magyar |
| 2018-02-16 | Update spec for rhs | Schuyler Eldridge |
| 2017-12-24 | Spec erroneously says mod instead of rem. | Paul Rigge |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-09-22 | Fixed width inference for add, sub (#312) | Adam Izraelevitz |
| 2016-08-17 | Change RW port names (#236) | Angie Wang |
| 2016-08-16 | Spec bugfix: update concrete reg syntax example (#233) | Adam Izraelevitz |
| 2016-07-27 | Fixed reg concrete syntax. #197. | azidar |
| 2016-05-23 | Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ju... | azidar |
| 2016-02-23 | Updated pdf | azidar |
| 2016-02-09 | Added license to FIRRTL files | azidar |
| 2016-02-09 | Added changes that addressed feedback, spec ready for release | azidar |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated todo list | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-23 | Added inference to mports | azidar |
| 2016-01-22 | Added a word | azidar |
| 2016-01-22 | Added funding number, as well as additional acknowledgements | azidar |
| 2016-01-22 | Finished version 0.2.0. Included leftovers for future user manual. | azidar |
| 2016-01-21 | First cut, some unfinished sections but readable | azidar |
| 2016-01-20 | WIP, almost finished with expressions. Removed poison, add is invalid and val... | azidar |
| 2016-01-20 | WIP: finished partial connect | azidar |
| 2016-01-19 | WIP: Writing new spec. | azidar |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks t... | azidar |
| 2016-01-16 | WIP | azidar |
| 2015-10-06 | Updated spec to mention sign extending widths of operand inputs | azidar |
| 2015-09-24 | Added poison node to spec | azidar |
| 2015-09-01 | Added cases of undefined behavior for cmem and smem | azidar |
| 2015-08-31 | Changed Bulk to Partial, <> to <-, and := to <= | azidar |
| 2015-08-31 | Updated spec | azidar |
| 2015-07-23 | Updated spec | azidar |
| 2015-07-22 | Minor updates to spec | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar |
| 2015-06-29 | Fixed minor typos. As of now, the finished version for internal feedback. | azidar |
