| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-08-31 | Updated spec | azidar | |
| 2015-07-23 | Updated spec | azidar | |
| 2015-07-22 | Minor updates to spec | azidar | |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar | |
| 2015-06-29 | Fixed minor typos. As of now, the finished version for internal feedback. | azidar | |
| 2015-06-26 | Changed clock from port kind to type | azidar | |
| 2015-06-26 | Finished draft of Version 0.1.3. Ready for comments. | azidar | |
| 2015-06-23 | More updates to spec | azidar | |
| 2015-06-22 | Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors | azidar | |
| 2015-06-12 | Added more changes to spec | azidar | |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar | |
| 2015-06-05 | Added most recent pdf | azidar | |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar | |
| 2015-04-08 | Finished expand whens. started infer widths. added pdf for people to view | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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