aboutsummaryrefslogtreecommitdiff
path: root/spec/spec.pdf
AgeCommit message (Collapse)Author
2020-04-13[spec] Add Fixed to spec (#1456)Albert Magyar
* [spec] Add Fixed to spec * Fixes #1195 * Define type & parameters * Add Fixed as argument type to type conversions * Add Fixed as argument type to relevent PrimOps (with link to tables) * Add asFixed PrimOp * Add IncP/DecP/SetP primops * Add fixed-point width/point propagation tables * Update spec pdf Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-26Update spec to clarify sign and use 'h' for hex throughoutAlbert Magyar
2020-03-13[spec] Update Mid FIRRTL spec to reflect removal of subaccesses (#1451)Albert Magyar
2020-03-02Update single-line when/else example in spec to match implementation (#1414)Albert Magyar
* Closes #890
2020-02-24[spec] clarify that div-by-zero is undefined (#1409)Albert Magyar
2020-02-11[spec] Change sub(UInt, UInt) output type to UInt (#1378)Albert Magyar
2020-02-06Add note to spec about reductions on zero-width wiresAlbert Magyar
2020-01-15improve the tail ir usability. (#1241)Sequencer
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
* Add spec for Analog type and attach statement * Describe role of attaches in partial connection algorithm * Change references that describe ground types where appropriate * Closes #1194 * Fix typo
2019-09-30Define read-write collison for independently clocked mem ports (#1188)Albert Magyar
* Define read-write collison for independently clocked mem ports * Included definition of initiating write/read operation
2019-09-16Update Spec from Gender to FlowSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
* Check mems for legal latencies; ban zero write latency. * Trigger
2019-07-30Make write-under-write section for mems in spec (#1140)Albert Magyar
2019-01-31Add MidFIRRTL spec (#1003)Albert Magyar
2018-09-27Number all code examples & add specification build to Makefile (#894)Ben Marshall
* Merge makefile changes from dev/specification-fixes - New top level makefile target: `specification` - Builds the specification document. * Number all code examples. This is more a change of convenience than anything. Referring to syntax examples is much easier when they are numbered! This commit is in the context of freechipsproject/firrtl#890 - Updating examples and syntax specification is made easier if they are numbered. - Change `verbatim` environments to `lstlisting` - Add very basic keyword highlighting. - Rebuild specification PDF. On branch dev/number-code-examples Changes to be committed: modified: spec/spec.pdf modified: spec/spec.tex
2018-02-16Update spec for rhsSchuyler Eldridge
Fixes #450 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-24Spec erroneously says mod instead of rem.Paul Rigge
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2016-07-27Fixed reg concrete syntax. #197.azidar
2016-05-23Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ↵azidar
just be a string. Removed symbols from identifiers except '_'
2016-02-23Updated pdfazidar
2016-02-09Added changes that addressed feedback, spec ready for releaseazidar
2016-01-22Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-memazidar
Conflicts: spec/spec.pdf
2016-01-22Added pdfazidar
2016-01-22Added funding number, as well as additional acknowledgementsazidar
2016-01-22Finished version 0.2.0. Included leftovers for future user manual.azidar
2016-01-21First cut, some unfinished sections but readableazidar
2016-01-20WIP, almost finished with expressions. Removed poison, add is invalid and ↵azidar
validif()
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵azidar
to be specified with write and rdwr mports
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP adding chirrtlazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2015-10-06Updated spec to mention sign extending widths of operand inputsazidar
2015-08-31Changed Bulk to Partial, <> to <-, and := to <=azidar
2015-08-31Updated specazidar
2015-07-23Updated specazidar
2015-07-22Minor updates to specazidar
2015-06-30Updated TODO. Ran spelling/grammar check on specazidar
2015-06-29Fixed minor typos. As of now, the finished version for internal feedback.azidar
2015-06-26Changed clock from port kind to typeazidar
2015-06-26Finished draft of Version 0.1.3. Ready for comments.azidar
2015-06-23More updates to specazidar
2015-06-22Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessorsazidar
2015-06-12Added more changes to specazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-05Added most recent pdfazidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-13Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bugazidar
2015-04-08Finished expand whens. started infer widths. added pdf for people to viewazidar
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-29 14:09:30 +0000