| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-01-31 | Add MidFIRRTL spec (#1003) | Albert Magyar | |
| 2018-09-27 | Number all code examples & add specification build to Makefile (#894) | Ben Marshall | |
| * Merge makefile changes from dev/specification-fixes - New top level makefile target: `specification` - Builds the specification document. * Number all code examples. This is more a change of convenience than anything. Referring to syntax examples is much easier when they are numbered! This commit is in the context of freechipsproject/firrtl#890 - Updating examples and syntax specification is made easier if they are numbered. - Change `verbatim` environments to `lstlisting` - Add very basic keyword highlighting. - Rebuild specification PDF. On branch dev/number-code-examples Changes to be committed: modified: spec/spec.pdf modified: spec/spec.tex | |||
| 2018-02-16 | Update spec for rhs | Schuyler Eldridge | |
| Fixes #450 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2017-12-24 | Spec erroneously says mod instead of rem. | Paul Rigge | |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz | |
| SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+). | |||
| 2016-07-27 | Fixed reg concrete syntax. #197. | azidar | |
| 2016-05-23 | Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ↵ | azidar | |
| just be a string. Removed symbols from identifiers except '_' | |||
| 2016-02-23 | Updated pdf | azidar | |
| 2016-02-09 | Added changes that addressed feedback, spec ready for release | azidar | |
| 2016-01-22 | Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-mem | azidar | |
| Conflicts: spec/spec.pdf | |||
| 2016-01-22 | Added pdf | azidar | |
| 2016-01-22 | Added funding number, as well as additional acknowledgements | azidar | |
| 2016-01-22 | Finished version 0.2.0. Included leftovers for future user manual. | azidar | |
| 2016-01-21 | First cut, some unfinished sections but readable | azidar | |
| 2016-01-20 | WIP, almost finished with expressions. Removed poison, add is invalid and ↵ | azidar | |
| validif() | |||
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar | |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵ | azidar | |
| to be specified with write and rdwr mports | |||
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar | |
| 2016-01-16 | WIP adding chirrtl | azidar | |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar | |
| 2015-10-06 | Updated spec to mention sign extending widths of operand inputs | azidar | |
| 2015-08-31 | Changed Bulk to Partial, <> to <-, and := to <= | azidar | |
| 2015-08-31 | Updated spec | azidar | |
| 2015-07-23 | Updated spec | azidar | |
| 2015-07-22 | Minor updates to spec | azidar | |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar | |
| 2015-06-29 | Fixed minor typos. As of now, the finished version for internal feedback. | azidar | |
| 2015-06-26 | Changed clock from port kind to type | azidar | |
| 2015-06-26 | Finished draft of Version 0.1.3. Ready for comments. | azidar | |
| 2015-06-23 | More updates to spec | azidar | |
| 2015-06-22 | Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors | azidar | |
| 2015-06-12 | Added more changes to spec | azidar | |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar | |
| 2015-06-05 | Added most recent pdf | azidar | |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar | |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar | |
| 2015-04-08 | Finished expand whens. started infer widths. added pdf for people to view | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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