| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-07-31 | Fixed typo in fixed-point type parameter examples (#1816) | Kevin Laeufer | |
| Co-authored-by: chick <chick@qrhino.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2020-07-15 | ir: store FileInfo string in escaped format (#1690) | Kevin Laeufer | |
| This should speed up the common case as the compiler never operates on the unescaped string. The new escape function also fixes a bug where ']' was not escaped even though it is the delimiting character for FileInfo. In order to maintain backwards compatibility for the ProtoBuf format, this patch adds escape/unescape calls when going from/to protobuf format. For better performance we should consider changing the protobuf format. | |||
| 2020-07-13 | [spec] Specify execution order of side-effect-having statements (#1724) | Albert Magyar | |
| * Define 'same clock' in a syntactic sense Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2020-07-09 | [spec] Explicitly disallow shadowing of component names (#1749) | Albert Magyar | |
| 2020-05-18 | Fix typo in spec description of 'tail' (#1626) | Albert Magyar | |
| * Closes #1597 | |||
| 2020-05-06 | Update spec.pdf | Schuyler Eldridge | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2020-04-13 | [spec] Add Fixed to spec (#1456) | Albert Magyar | |
| * [spec] Add Fixed to spec * Fixes #1195 * Define type & parameters * Add Fixed as argument type to type conversions * Add Fixed as argument type to relevent PrimOps (with link to tables) * Add asFixed PrimOp * Add IncP/DecP/SetP primops * Add fixed-point width/point propagation tables * Update spec pdf Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2020-03-26 | Update spec to clarify sign and use 'h' for hex throughout | Albert Magyar | |
| 2020-03-13 | [spec] Update Mid FIRRTL spec to reflect removal of subaccesses (#1451) | Albert Magyar | |
| 2020-03-02 | Update single-line when/else example in spec to match implementation (#1414) | Albert Magyar | |
| * Closes #890 | |||
| 2020-02-24 | [spec] clarify that div-by-zero is undefined (#1409) | Albert Magyar | |
| 2020-02-11 | [spec] Change sub(UInt, UInt) output type to UInt (#1378) | Albert Magyar | |
| 2020-02-06 | Add note to spec about reductions on zero-width wires | Albert Magyar | |
| 2020-01-15 | improve the tail ir usability. (#1241) | Sequencer | |
| Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2019-11-13 | Add spec for Analog type and attach statement (#1222) | Albert Magyar | |
| * Add spec for Analog type and attach statement * Describe role of attaches in partial connection algorithm * Change references that describe ground types where appropriate * Closes #1194 * Fix typo | |||
| 2019-09-30 | Define read-write collison for independently clocked mem ports (#1188) | Albert Magyar | |
| * Define read-write collison for independently clocked mem ports * Included definition of initiating write/read operation | |||
| 2019-09-16 | Update Spec from Gender to Flow | Schuyler Eldridge | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2019-08-07 | Check mems for legal latencies; ban zero write latency. (#1147) | Albert Magyar | |
| * Check mems for legal latencies; ban zero write latency. * Trigger | |||
| 2019-07-30 | Make write-under-write section for mems in spec (#1140) | Albert Magyar | |
| 2019-01-31 | Add MidFIRRTL spec (#1003) | Albert Magyar | |
| 2018-09-27 | Number all code examples & add specification build to Makefile (#894) | Ben Marshall | |
| * Merge makefile changes from dev/specification-fixes - New top level makefile target: `specification` - Builds the specification document. * Number all code examples. This is more a change of convenience than anything. Referring to syntax examples is much easier when they are numbered! This commit is in the context of freechipsproject/firrtl#890 - Updating examples and syntax specification is made easier if they are numbered. - Change `verbatim` environments to `lstlisting` - Add very basic keyword highlighting. - Rebuild specification PDF. On branch dev/number-code-examples Changes to be committed: modified: spec/spec.pdf modified: spec/spec.tex | |||
| 2018-02-16 | Update spec for rhs | Schuyler Eldridge | |
| Fixes #450 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2017-12-24 | Spec erroneously says mod instead of rem. | Paul Rigge | |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz | |
| SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+). | |||
| 2016-07-27 | Fixed reg concrete syntax. #197. | azidar | |
| 2016-05-23 | Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ↵ | azidar | |
| just be a string. Removed symbols from identifiers except '_' | |||
| 2016-02-23 | Updated pdf | azidar | |
| 2016-02-09 | Added changes that addressed feedback, spec ready for release | azidar | |
| 2016-01-22 | Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-mem | azidar | |
| Conflicts: spec/spec.pdf | |||
| 2016-01-22 | Added pdf | azidar | |
| 2016-01-22 | Added funding number, as well as additional acknowledgements | azidar | |
| 2016-01-22 | Finished version 0.2.0. Included leftovers for future user manual. | azidar | |
| 2016-01-21 | First cut, some unfinished sections but readable | azidar | |
| 2016-01-20 | WIP, almost finished with expressions. Removed poison, add is invalid and ↵ | azidar | |
| validif() | |||
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar | |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵ | azidar | |
| to be specified with write and rdwr mports | |||
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar | |
| 2016-01-16 | WIP adding chirrtl | azidar | |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar | |
| 2015-10-06 | Updated spec to mention sign extending widths of operand inputs | azidar | |
| 2015-08-31 | Changed Bulk to Partial, <> to <-, and := to <= | azidar | |
| 2015-08-31 | Updated spec | azidar | |
| 2015-07-23 | Updated spec | azidar | |
| 2015-07-22 | Minor updates to spec | azidar | |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar | |
| 2015-06-29 | Fixed minor typos. As of now, the finished version for internal feedback. | azidar | |
| 2015-06-26 | Changed clock from port kind to type | azidar | |
| 2015-06-26 | Finished draft of Version 0.1.3. Ready for comments. | azidar | |
| 2015-06-23 | More updates to spec | azidar | |
| 2015-06-22 | Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors | azidar | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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