| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-11-16 | Make Yosys equivalence check more robust (#686) | Jack Koenig | |
| Also let Travis know that equivalence checks can take a while | |||
| 2017-10-01 | Add script for formally comparing emitted Verilog | Jack Koenig | |
| Also add Travis test for running this script on PRs | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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