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2018-06-15Improve Parser and Visitor (#819)Jack Koenig
* Update Parser to use ANTLR CharStreams This removes some unnecessary object creation in String reading and manipulation * Remove two unnecessary traversals from Block construction in Visitor
2018-06-14Fix TopWiringTests use of /tmp. (#825)Jim Lawson
Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
Candidate fix for #749 This adds DefRegister netlist ordering to RemoveWires Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-12Deprecate SingleStringAnnotation (#811)Jack Koenig
It does not provide anything over NoTargetAnnotation. Its existence suggests some significance so removing it for clarity.
2018-06-11Allow escaped single quotes in RawParams (#820)Richard Lin
Escape raw params using \'
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
Also minor cleanup to literal construction in Visitor
2018-06-11Use attach to connect analogs when grouping (#805)Colin Schmidt
2018-06-11Fix some typos in leftovers.txt (#822)Felix Yan
2018-06-10ucb-bar -> freechipsproject in clone instructionLeonard (Lenny) Truong
2018-06-08Add a blacklist option for paths (#810)Colin Schmidt
Useful if you want to find out how a node was reachable and you used a blacklist during the reachability analysis
2018-06-06Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)Chick Markley
Add optional argument to verilogToCpp to suppress VCD
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
This enables the pattern of attaching "through" a wire to give better Verilog that also works in Verilator Use WrappedExpression when combining attaches in ExpandWhens to ensure no duplication of references in resulting, combined attaches
2018-05-30Merge pull request #816 from freechipsproject/expand-when-preserve-info-1Jack Koenig
Makes ExpandWhens preserve connect Infos Also fix Travis regressions
2018-05-30Improve Travis configuration and revert Yosys versionJack Koenig
* Switch Yosys back to 0.7 with patch for moved ABC repo * Add 30 min timeout for LEC tests * h/t https://stackoverflow.com/questions/43918874#44007537 * Move Travis building of Verilator and Yosys to prelude stage * Don't use automatic Travis Scala tests, do it manually
2018-05-30Makes ExpandWhens preserve connect Infoschick
* Collects Infos found for symbols * Merges multiple sources for symbol into MultiInfo * Restores these Infos on connect statements. * Add test showing preserved Infos * Changed ++ methods on the Info sub-classes * Ignore NoInfo being added * Fixed way adding was implemented in MultiInfo * Made InfoMap a class which defines the default value function
2018-05-29Fix pad (#817)Jack Koenig
* Make VerilogEmitter properly handle pad of width <= width of arg * Constant prop pads with pad amount <= width of arg
2018-05-23Add Circuit as option to FirrtlOptions (#814)Jack Koenig
2018-05-21Fix more problems with zero width things. (#779)grebe
This should close #757. It should also allow for stop() and printf() to be used with zero-width fields.
2018-05-17Change from Yosys 0.7 to master (#812)Jack Koenig
Yosys 0.7 build is broken because ABC moved repos and the link no longer works
2018-05-16Bump version of Verilator used in Travis to 3.922 (#784)Jack Koenig
2018-05-15Don't use bash to determine command availability - fixes #807 (#808)Jim Lawson
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog.
2018-05-11TopWiring Transform (#798)alonamid
* top wiring transform * fixup comments * TopWiring cosmetics * move prefix into TopWiringAnnotation * remove test function from transform file * add ChildrenMap to InstanceGraph API * use namespaces * remove wiringUtils from TopWiring pass * enable multiple output functions * TopWiring cosmetics, tests and lowform
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
The following are deprecated in favor of DiGraph/InstanceGraph: - firrtl.passes.wiring.Lineage - firrtl.passes.wiring.WiringUtils.ChildrenMap - firrtl.passes.wiring.WiringUtils.getChildrenMap - firrtl.passes.wiring.WiringUtils.getLineage Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-04-29Fix pathological behavior of Namespace for name collisions (#788)Jack Koenig
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
* Change VerilogMemDelays to put new Statements at end of Module Fixes #547 This is instead of putting them right after the modified DefMemory which could result in use before declaration errors for things that feed into the new logic. * Adds tests that show VerilogMemDelays crashing. (#792)
2018-04-16Cleaning up BlackBoxSourceHelper - use absolute file paths. (#789)Jim Lawson
* Cleaning up BlackBoxSourceHelper - use absolute file paths. ```bash make[1]: *** No rule to make target `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v', needed by `/Users/john/chisel-testers/test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/VAccumBlackBoxWrapper.h'. Stop. ``` since the path `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v` does not exist inside `test_run_dir`. We should either: - strip the targetDir prefix, - prepend a `../` to the path, - use absolute paths I decided to go with the latter since this makes the least assumptions about the actual downstream processing and we already use absolute paths in other parts of this code. * Minor cleanup. - Anonymize make failure comment. - Use common map syntax.
2018-04-13Remove infinitely recursive function (#790)Jack Koenig
h/t @sdtwigg
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
Create sources once per module, not once per instance Clean up writing the file list Don't prepend file list with '-v's (non-standard and not all verilog) Change file list file name (not all verilog) Use ListSets for determinism
2018-04-11Make DiGraph.linearize be iterative instead of recursive (#785)Jack Koenig
Also make DiGraphTests more ScalaTest-y
2018-04-10Fix bug in Constant Propagation for registers propped to zero (#787)Jack Koenig
It wasn't properly padding the width of the constant zero. Also add a test that shows the buggy behavior.
2018-04-03Make Dedup properly dedup ExtModules (#781)Jack Koenig
2018-04-02CyclicException identifies a problem node. (#778)Chick Markley
Needed for special handling in Treadle. Small refactor that allows users of DiGraph#linearize to return the first node found in a cycle. Fixed RemoveWiresTransfrom to handle this. Added test to show usage of this feature.
2018-03-28Enhance RenameMap to support circuit renaming (#775)Jack Koenig
Also delete CircuitTopName. It will not work with updated RenameMap
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
Moved from RemoveValidIf Also Make RemoveValidIf.getGroundZero public and support Fixed
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-27Const prop improvement (#772)Jack Koenig
Improve constant propagation of connections to references [skip formal checks] LEC fails on this PR because this PR actually changes the circuit. The change is that it constant propagates some additional registers. This is really just extending #621 to work on more registers that it was supposed to be propagating anyway.
2018-03-26Make WiringTransform remove its used annotations (#774)Schuyler Eldridge
* Make WiringTransform remove its used annotations Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-23Make Register Update Flattening a Transform and Delete Dangling Nodes (#692)Jack Koenig
2018-03-22Better bad annotation file error reporting (#771)Jack Koenig
* Propagate exceptions from JsonProtocol deserialization * Add AnnotationFileNotFoundException for better error reporting * Add AnnotationClassNotFoundException for better error reporting * Better propagate JSON parsing errors Also report the file if there is a error deserializing a JSON file * Make exception for non-array JSON file more explicit
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
* Added grouping pass * Added InfoMagnet and infomappers * Changed return type of execute to allow final CircuitState inspection * Updated dedup. Now is name-agnostic * Added GroupAndDedup transform
2018-03-21Add SyntaxErrorsException as a type of ParserException (#770)Jack Koenig
Also make ParserException extend FIRRTLException to better report parsing errors to the user
2018-03-20Correct extmodule example in spec (#768)Albert Magyar
2018-03-19Adding the firrtl proto. (#746)Kevin Townsend
* Adding the firrtl proto. * .
2018-03-19Pass up annotations in return value from Driver.execute (#760)Chick Markley
* Pass up annotations in return value from Driver.execute Backward compatible with existing usage. Adds CircuitState to FirrtlExecutionSuccess, but that member is not part of the unapply. "To a single file per module if OneFilePerModule is specified" test shows example of getting access to annotations * As experiment return created files in annotations Fix line missed in last push
2018-03-19Update README.md (#761)Albert Magyar
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
Closes #666.
2018-03-15Improve section heading (#762)edwardcwang
2018-03-03Bump SNAPSHOT version (#752)Jim Lawson
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