| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-02 | Merge pull request #215 from ucb-bar/new-serialize | Adam Izraelevitz | |
| Change serialize to abstract method on FirrtlNode | |||
| 2016-08-02 | Merge pull request #203 from ucb-bar/fix_mem_infer | Adam Izraelevitz | |
| Fix mem infer | |||
| 2016-08-02 | make infer readwrite ports optional | Donggyu Kim | |
| turned on with '--inferRW <circuit name>' | |||
| 2016-08-02 | Change serialize to abstract method on FirrtlNode | Jack Koenig | |
| 2016-08-02 | Merge pull request #214 from ucb-bar/fix-thread-unsafety | Adam Izraelevitz | |
| Fix use of global state in instance loop checking | |||
| 2016-08-02 | Merge pull request #213 from ucb-bar/default-to-warn | Adam Izraelevitz | |
| Change default log level to warn | |||
| 2016-08-02 | Merge pull request #211 from ucb-bar/fix-subaccess | Adam Izraelevitz | |
| Refactor RemoveAccesses and fix bug #210. | |||
| 2016-08-02 | Fix use of global state in instance loop checking | jackkoenig | |
| Also increase sensitivity of thread safety checking Fixes #159 | |||
| 2016-08-01 | Merge pull request #208 from ucb-bar/no_constprop | Adam Izraelevitz | |
| remove ConstProp in HighFirrtlToMiddleFirrtl | |||
| 2016-08-01 | Merge pull request #212 from ucb-bar/fix-validChar | Adam Izraelevitz | |
| Fix StringSpec generators to only choose from valid values. | |||
| 2016-08-01 | Added minor cosmetic changes to RemoveAccesses | azidar | |
| 2016-08-01 | Change default log level to warn | Jack Koenig | |
| 2016-08-01 | Refactor RemoveAccesses and fix bug #210. | azidar | |
| Added corresponding unit test. | |||
| 2016-08-01 | Fix StringSpec generators to only choose from valid values. | Jack Koenig | |
| The old almost equivalent syntax gives the same result but can cause the test to fail if too many invalid values are thrown away. | |||
| 2016-07-29 | remove ConstProp in HighFirrtlToMiddleFirrtl | Donggyu Kim | |
| ConstProp before width padding causes errors for SIntLiteral | |||
| 2016-07-28 | Merge pull request #207 from ucb-bar/fix-width-bug | Donggyu | |
| InferWidths now only fixes declaration widths | |||
| 2016-07-28 | InferWidths now only fixes declaration widths | azidar | |
| Then calls InferTypes to propagate inferred widths to expressions. Required upgrading InferTypes to do simple width propagation. Fixes #206 and #200. | |||
| 2016-07-27 | infer readwrite ports for backward compatibility | Donggyu Kim | |
| 2016-07-27 | fix read port enables in RemoveCHIRRTL | Donggyu Kim | |
| read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced | |||
| 2016-07-27 | Merge pull request #205 from ucb-bar/add-future-release | Adam Izraelevitz | |
| Added future-release.txt | |||
| 2016-07-27 | Merge pull request #199 from ucb-bar/add-annotations | Adam Izraelevitz | |
| Rework Annotations | |||
| 2016-07-27 | Fixed compilation error using old annotations | azidar | |
| 2016-07-27 | Forgot to add Annotations.scala | Adam Izraelevitz | |
| 2016-07-27 | Reworked annotation system. Added tenacity and permissibility | Adam Izraelevitz | |
| Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala | |||
| 2016-07-27 | Merge pull request #204 from ucb-bar/fix-spec | Adam Izraelevitz | |
| Fixed reg concrete syntax. #197. | |||
| 2016-07-27 | Added future-release.txt | azidar | |
| Keeps track of proposed changes to add to the next version of the Firrtl spec. | |||
| 2016-07-27 | Merge pull request #198 from ucb-bar/add-chirrtl-check | Adam Izraelevitz | |
| Added a Chirrtl check for undeclared wires, etc. | |||
| 2016-07-27 | Fixed reg concrete syntax. #197. | azidar | |
| 2016-07-26 | Merge pull request #201 from ucb-bar/recursive-modules-fix | Adam Izraelevitz | |
| Detects and flags cyclic module loops | |||
| 2016-07-25 | Changed InferTypes to update types if UnknownType or has an UnknownWidth | azidar | |
| Removed InferWidths after ExpandWhens | |||
| 2016-07-25 | Detects and flags cyclic module loops | chick | |
| 2016-07-21 | Added a Chirrtl check for undeclared wires, etc. | azidar | |
| 2016-07-21 | Indentation support for the ANTLR parser (as discussed in #192) (#194) | Kamyar Mohajerani | |
| Indentation support for the ANTLR parser - some clean-up of the parser code (TODO: file input could be improved, more clean-up) - get rid of Translator and specify all syntactic rules in antlr4 grammer - support for else-when shorthand in the grammar - rename Begin to Block which makes more sense | |||
| 2016-07-07 | Guard register randomization with RANDOMIZE, rather than SYNTHESIS | Andrew Waterman | |
| Randomization should be controllable separately. Verilator, for example, already does this if it is passed --x-assign unique; doing it redundantly reduces simulation performance. | |||
| 2016-07-07 | Re-run constant propagation after pad widths | Andrew Waterman | |
| 2016-07-07 | Generalize and clean up constant propagation pass | Andrew Waterman | |
| 2016-07-06 | Emit correct Verilog for SIntLiteral | Andrew Waterman | |
| 2016-07-06 | Only assign garbage to Mem reads for non-power-of-2 depths | Andrew Waterman | |
| 2016-07-06 | Avoid width warnings on Mem garbage assignment | Andrew Waterman | |
| 2016-07-06 | Rely on $fatal vs. $finish, rather than stderr, for stop codes | Andrew Waterman | |
| This approach uses the normal Unix mechanisms, rather than log grepping. | |||
| 2016-07-05 | Merge pull request #195 from terpstra/support-char-printf | Adam Izraelevitz | |
| printf: support '%c' for printing characters | |||
| 2016-07-04 | printf: support '%c' for printing characters | Wesley W. Terpstra | |
| 2016-06-27 | Optionally guard stop with `STOP_COND macro | Andrew Waterman | |
| This allows for testbench handling of pipelined reset, independently of `PRINTF_COND. | |||
| 2016-06-23 | Emit more useful code for stop | Andrew Waterman | |
| - Based upon stop value, use $fatal instead of $finish. This causes the Verilog simulator to signal an error to the OS as appropriate. - Don't guard stop with `PRINTF_COND (only not-`SYNTHESIS). | |||
| 2016-06-13 | Merge pull request #191 from ucb-bar/ir-cleanup-fix | Adam Izraelevitz | |
| Ir cleanup fix | |||
| 2016-06-10 | Change BoolType from method to val | Jack Koenig | |
| 2016-06-10 | API Cleanup - AST | Jack | |
| trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._ | |||
| 2016-06-10 | API Cleanup - PrimOp & PrimOps | Jack | |
| Add simple documentation trait PrimOp -> abstract class PrimOp Move PrimOp case objects to object PrimOps Rename PrimOp case objects to match concrete syntax Overrwrite toString for more canonical serialization Update some PrimOps utility functions | |||
| 2016-06-10 | API Cleanup - Expression | Jack | |
| trait Expression -> abstract class Expression Ref -> Reference abbrev. exp -> expr Add abstract class Literal UIntValue -> UIntLiteral extends Literal SIntValue -> SIntLiteral extends Literal | |||
| 2016-06-10 | API Cleanup - Statement | Jack | |
| trait Stmt -> abstract class Statement (to match Expression) abbrev. exp -> expr BulkConnect -> PartialConnect camelCase things that were snake_case case class Empty() -> case object EmptyStmt Change >120 character Statements to multiline | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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