aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2015-08-25Added width check pass with tests. #22.azidar
2015-08-24Temporarily deprecated the flo backend until I fix itazidar
2015-08-24Added BigInt error if passed a string without starting with a b or hazidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-24Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵azidar
now be small examples, categorized by either passes, errors, or features.
2015-08-20Updated .gitignoreazidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-20Added rsh test for const-propazidar
2015-08-20Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19.azidar
2015-08-20Fixed bigint library to correctly extract bits from UIntValue. #19.azidar
2015-08-19Added new const propagation testazidar
2015-08-19Added beginning of constant propagation pass, doesn't workazidar
2015-08-19Switched to new bigint libraryazidar
2015-08-19Check Neg UInt in the parserazidar
2015-08-19Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-08-19Fixed width inference bug where constraints were propagating backwards.azidar
Updated tests to match. #29.
2015-08-19Fixed width inference bug where constraints were propagating backwards. ↵azidar
Updated tests to match.
2015-08-18Updated shr test so it is an expected passazidar
2015-08-18Fixed width inference for static shift left, #18azidar
2015-08-18Fixed verilog emission from rand to randomazidar
2015-08-18Fixed bug in MinusWidth where it was adding instead of subtracting widthsazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be ↵azidar
extract, not >>
2015-08-18Emit random initialization instead of zero initialization for Verilog regazidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
an optimization that eliminated some when statements. Added test case.
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-05Added type inference before gender checkazidar
2015-08-05Fixed bug in temp elimination.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added () around width printersazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
invalid <> assignments.
2015-08-03Added concrete syntax for EmptyStmt()azidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Fixed (?) resolve genders passazidar
2015-07-31Reading from output ports no longer causes errorsazidar
2015-07-31Fixed inferred type of bits and bitazidar
2015-07-31Fixed compiletime error, whooopsazidar
2015-07-31Allow bit operations on sintsazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-31Merge pull request #12 from ucb-bar/make-depsAdam Izraelevitz
Fix makefile dependences so make -j doesn't fail
2015-07-30Added module name to error messages.azidar
2015-07-30Merge branch 'new-low-firrtl'azidar
2015-07-30Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-03 14:26:45 +0000