| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-10-01 | Add Yosys 0.7 install | Jack Koenig | |
| 2017-10-01 | Remove redundant tests from Travis | Jack | |
| 2017-09-30 | Make ReplaceAccesses optimize multi-dimensional accesses (#665) | Albert Magyar | |
| 2017-09-30 | Update README.md to link tech report (#550) | Adam Izraelevitz | |
| 2017-09-30 | Fixed zero width cat but (#651) | Adam Izraelevitz | |
| 2017-09-29 | StringLit.verilogEscape should support all printable ASCII chars (#668) | Jack Koenig | |
| Defined as the range from ' ' to '~' [0x20, 0x7e] | |||
| 2017-09-29 | Namespace - only save suffix for temp names (#667) | Jack Koenig | |
| This prevents collisions for one prefix (including temp) from incrementing the suffix for other prefixes. Makes names more stable. | |||
| 2017-09-22 | Fix string lit (#663) | Jack Koenig | |
| Refactor StringLit to use String instead of Array[Byte] | |||
| 2017-09-21 | Some ScalaDoc warning fixes | Edward Wang | |
| 2017-09-21 | Fix problem where wrong verilog file is used. (#661) | Chick Markley | |
| When calling verilator in a subdirectory like ./test_run_dir/... verilator will read the verilog file from the current working directory if there is a file there with the right name. This fix specifies the specific path of the verilog file intended. | |||
| 2017-09-19 | Provide mechanism so that programs can optionally (#660) | Chick Markley | |
| not exit when --help is included in program flags | |||
| 2017-09-19 | Create way of collecting program arguments in Driver (#659) | Chick Markley | |
| Adds programArgs to commonOptions programArgs is all arguments on command line with out leading -/+ or are not bound to a flag. Create simple test | |||
| 2017-09-14 | Update sbt to 0.13.16; add Scala 2.12 support. (#639) | Jim Lawson | |
| * Update sbt to 0.13.16; add Scala 2.12 support. To clean, test, and build Scala 2.11 and Scala 2.12 versions: % sbt +clean +test +publishLocal * Update Travis to test in 2.11.11 and 2.12.3 * Try different way of providing Travis Scala version * Attempt to get verilator built before tests. | |||
| 2017-09-12 | Make pathsInDAG walk all possible paths (#655) | Schuyler Eldridge | |
| * Make pathsInDAG walk all possible paths Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use linearization order when finding all paths in DAG | |||
| 2017-09-06 | Write tests on multi-rooted circuits for ConstProp | Edward Wang | |
| Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour. - Need to think about how to target ConstProp only for a specific module? Close #644 | |||
| 2017-09-05 | Add InstanceGraph tests | Edward Wang | |
| 2017-09-05 | Make InstanceGraph track module hierarchies not contained in the top-level ↵ | Albert Magyar | |
| hierarchy | |||
| 2017-08-31 | Added option to emit final annotations (#649) | Adam Izraelevitz | |
| * Added option to emit final annotations * Removed extra > from output-anno-file * Removed other extra > from input-anno-file | |||
| 2017-08-23 | Reorder port and wire assignments in Verilog (#641) | Adam Izraelevitz | |
| * Reorder port and wire assignments in Verilog * Fixed up syntax | |||
| 2017-08-14 | Constant propagation across module boundaries (#633) | Jack Koenig | |
| 2017-08-04 | bug fix for cases when we want to flatten a module in which a module is ↵ | Andrey Ayupov | |
| instantiated multiple times (#634) | |||
| 2017-08-01 | DCE for IsInvalid (#629) | Donggyu | |
| 2017-07-26 | Flatten transformation (#631) | Andrey Ayupov | |
| * initial implementation of InlineDeepTransformation * rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined * minor rewrites * renamed transformations to Flatten * fixes according to review * added more comments and fixed formating/style * fixed spacing, minor style fixes | |||
| 2017-07-18 | Merge pull request #626 from freechipsproject/fix-swap-bug | Jack Koenig | |
| Fix ConstProp bug where multiple names would swap with one | |||
| 2017-07-17 | do not swap wire names with node names | Donggyu Kim | |
| 2017-07-17 | Fix ConstProp bug where multiple names would swap with one | Jack Koenig | |
| Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848 | |||
| 2017-07-14 | Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628) | Jack Koenig | |
| 2017-07-06 | Fixed inability to disable combo loop check (#619) | Chick Markley | |
| * Fixed inability to disable combo loop check Moved checking of dontCheckComboLoops into loadAnnotations so that it works in cases where Driver.execute is not used. * Fix test for annotations, modifications to loadAnnotations made 2 more annotations visible. * Remove debug println from DriverSpec | |||
| 2017-07-03 | Merge pull request #621 from freechipsproject/const-prop-regs | Jack Koenig | |
| Const prop regs | |||
| 2017-06-29 | ConstProp registers that are only connected to or reset to a consant | Jack Koenig | |
| 2017-06-29 | Connect registers with no connections to zero | Jack Koenig | |
| 2017-06-29 | Add test for padding constant connections to wires in ConstProp | Jack Koenig | |
| 2017-06-29 | Merge pull request #620 from freechipsproject/keep-names | Jack Koenig | |
| Preserve "better" names in Constant Propagation | |||
| 2017-06-29 | Preserve "better" names in Constant Propagation | Jack Koenig | |
| Names that do not start with '_' are "better" than those that do | |||
| 2017-06-29 | Merge pull request #616 from freechipsproject/split-travis | Jack Koenig | |
| Use Travis Build Stages | |||
| 2017-06-29 | [Travis] Explicitly limit chisel tests parallelism to 2 | Jack | |
| 2017-06-29 | [Travis] Use Build Stages | Jack | |
| 2017-06-29 | Merge pull request #617 from freechipsproject/const-prop-regs | Jack Koenig | |
| Improvements to Constant Propagation and Testing | |||
| 2017-06-28 | Make Constant Propagation respect dontTouch | Jack Koenig | |
| Constant Propagation will not optimize across components marked dontTouch | |||
| 2017-06-28 | Promote ConstProp to a transform | Jack Koenig | |
| 2017-06-28 | [Testing] Clean up SimpleTransformSpec execute methods | Jack Koenig | |
| This makes it more concise to write tests | |||
| 2017-06-28 | [Testing] Have SimpleTransformSpec mix in FirrtlMatchers | Jack Koenig | |
| Gives all transform specs access to useful utilities (like dontTouch). Deletes some duplicate code. Parsing mode UseInfo is fine for everything, only matters if the test actually uses info. | |||
| 2017-06-28 | Merge pull request #615 from freechipsproject/remove-reset | Jack Koenig | |
| Remove reset and fix bug in register update Verilog emission | |||
| 2017-06-27 | Add RemoveReset transform to replace register reset with a Mux | Jack Koenig | |
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig | |
| Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update. | |||
| 2017-06-26 | Add support for wires in ConstProp | Jack Koenig | |
| This requires a quick second pass to back propagate constant wires but the QoR win is substantial. We also only need to count back propagations in determining whether to run ConstProp again which shaves off an iteration in the common case. | |||
| 2017-06-26 | Speed up ConstProp by doing ConstProp before recording node | Jack Koenig | |
| Similar to #543 | |||
| 2017-06-21 | Add --no-dce command-line option to skip DCE | Jack Koenig | |
| 2017-06-13 | Replace IsInvalids on LowForm with connection to zero | Jack Koenig | |
| 2017-06-13 | Canonicalize spacing in RemoveValidIf | Jack Koenig | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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