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2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-22Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-22Added pdfazidar
2016-01-22Added a wordazidar
2016-01-22Added funding number, as well as additional acknowledgementsazidar
2016-01-22Finished version 0.2.0. Included leftovers for future user manual.azidar
2016-01-21First cut, some unfinished sections but readableazidar
2016-01-20WIP, almost finished with expressions. Removed poison, add is invalid and val...azidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-20WIP: finished partial connectazidar
2016-01-19WIP: Writing new spec.azidar
2016-01-17Forgot to add the changesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ...azidar
2016-01-17Added check for uint on access index typeazidar
2016-01-17Removed temporary filesazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Add warning that -p unusedducky
2016-01-16Clean up old logging remnantsducky
2016-01-16Merge branch 'scala-new-mem' of github.com:ucb-bar/firrtl into scala-new-memducky
2016-01-16Ignore eclipse .projectducky
2016-01-16Import a logging library so we don't reinvent the wheel and have implicits fl...ducky
2016-01-16Refactor passes systemducky
2016-01-16Default platform-agnostic, ignore platform-specific FileCheckducky
2016-01-16Update README with better Linux and Scala instructionsducky
2016-01-16Added notes for Richard to work onazidar
2016-01-16Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-memazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Standard Verilog doesn't use Resolve(), but lists out the resolution passes i...azidar
2016-01-16Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-memazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Added notes for Richard to work onazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
2016-01-16Fixed bug in lowering memories that had aggregate data typesazidar
2016-01-16Fixed bug in check-init that allows it to check on non-lowered thingsazidar
2016-01-16Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat...azidar
2016-01-16Nodes must now be ground typesazidar
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Fixed Vector performance testsazidar
2016-01-16Reworked Verilog emission of registers to if/else instead of ?:azidar
2016-01-16No longer split on muxesazidar
2016-01-16Commented back in Starting and Finishing for testingazidar
2016-01-16Sped up remove access by checking a conditionazidar
2016-01-16Added more data in printout of time to compileazidar
2016-01-16printf no longer includes a new lineazidar
2016-01-16Verilog emission no longer casts input to shr or bit selectazidar
2016-01-16Added hashed on get flipazidar
2016-01-16Sped up some passes. Added global mname to allow easy per-module hashes for a...azidar
2016-01-16Made create-exps a bit fasterazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks t...azidar
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