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2021-07-25Add typedef in DependencyManager.Jiuyang Liu
This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile: ``` class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) { override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq( Dependency[DedupModules] ) } ```
2021-07-14Fix memory annotation deduplication (#2286)Jared Barocsi
* Add transform to deduplicate memory annotations * Add annotation deduplication to Dedup stage * ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform * Verilog emitter now throws exception when memory annotations fail to dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-12Update sbt to 1.5.5 (#2292)Scala Steward
2021-07-11Rm java.io in WriteEmitted (#2275)sinofp
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-11Update sbt to 1.5.4 (#2267)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-11Deprecate BlackBoxResourceAnno (#2262)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-11Merge pull request #2290 from scala-steward/update/sbt-scalafmt-2.4.3Jiuyang Liu
Update sbt-scalafmt to 2.4.3
2021-07-09Update sbt-scalafmt to 2.4.3Scala Steward
2021-07-07Replace hard coded line separators with system specific ones (#2281)Boyang Han
2021-07-06Merge pull request #2285 from ↵Schuyler Eldridge
chipsalliance/dev/seldridge/spec-zero-width-select-mux Relax spec on 0-bit mux select, use SFC behavior
2021-06-30Relax spec on 0-bit mux select, use SFC behaviorSchuyler Eldridge
Change the FIRRTL specification document to allow for 0-bit mux selects. The existing ZeroWidths pass will promote these to a 1-bit, 0-valued select signal (which effectively means that the mux can be optimized away to just the false path). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-25Correct a typo in src/main/scala/firrtl/WIR.scala (#2283)Felix Yan
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
The pass injects pipe registers immediately after the declaration of the memory. This can be problematic if the clock for the associated memory port is defined after the declaration of the memory. For any memory port clocks that are driven by non-ports, we now inject a wire before the pipe register declarations to be sure there are no use-before-declaration issues.
2021-06-21[spec] Explicit widths may be non-negative, not just positive (#2277)Albert Magyar
* Fixes #2206
2021-06-18Fix MultiInfo parser + serialization bug (#2265)Jared Barocsi
* Restore parsed MultiInfo structure in firrtl parser * Change erroneous expected output in InfoSpec test FileInfo compression sorts the outputted entries alphabetically, but this test did not reflect that fact * Fix typo in comment * Add unit tests for file locator parsing * Fix syntax issues and typos * More redundant braces removed Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-17smt: include firrtl statement names in SMT and btor2 output (#2270)Kevin Laeufer
* smt: include firrtl statement names in SMT and btor2 output * smt: remove println * smt: make tests run again and fix stale ones Apparently `private` classes aren't found by th sbt test runner.
2021-06-17Add --start-from option (#2273)Schuyler Eldridge
Add a new option to the FIRRTL compiler, "--start-from = <form>". If used, this will cause the compiler to assume that the input FIRRTL circuit is already in the specific form. It will then skip unnecessary passes given this information. E.g., if a user requests to run "firrtl -X verilog --start-from low" then the compiler will only run transforms necessary to get from low FIRRTL to Verilog. Transforms necessary for ingesting FIRRTL IR will be run if needed (checks and type/kind/flow resolution). To implement this, a CurrentFirrtlStateAnnotation is added. Advanced users can use this directly to tell the FIRRTL compiler exactly what transforms have already been run, including the ability to ignore checks or type/kind/flow resolution if they so desire. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-17Add Protocol Buffer emission (#2271)Schuyler Eldridge
* Add Protocol Buffer emission export This adds infrastructure and annotations that let a user emit a FIRRTL circuit as a Protocol Buffer. Fixes #1696. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add Protocol Buffer emission export
2021-06-15make PresetRegAnnotation public (#2254)Kevin Laeufer
* make PresetRegAnnotation public this annotation is useful outside the firrtl compiler: - to implement a pass that creates registers which need to be initialized at the beginning of simulation (e.g., for formal verification) - to support preset registers in treadle * add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
2021-06-14Add -X mhigh compiler for minimal high form (#2268)Schuyler Eldridge
Add a compiler/emitter that can target minimal high form. This will produce output that only has CHIRRTL constructs removed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-09Merge pull request #2263 from sinofp/nomorejavaio-mustdedupJiuyang Liu
Remove java.io in MustDedup
2021-06-08Prepend target dir to default dedup report dirsinofp
Requested by reviewer.
2021-06-08Rm java.io in MustDedupsinofp
2021-06-08Merge pull request #2256 from sinofp/nomorejavaio-fileutilsJiuyang Liu
Remove java.io in FileUtils
2021-06-06Merge branch 'master' into nomorejavaio-fileutilsJiuyang Liu
2021-06-06Merge pull request #2258 from scala-steward/update/os-lib-0.7.8Jiuyang Liu
Update os-lib to 0.7.8
2021-06-05Merge branch 'master' into update/os-lib-0.7.8mergify[bot]
2021-06-05Add deprecation annotation in FileUtilssinofp
2021-06-04Update sbt-scoverage to 1.8.2 (#2261)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-06-04Merge branch 'master' into update/os-lib-0.7.8Jiuyang Liu
2021-06-04Merge pull request #2257 from scala-steward/update/sbt-scalafix-0.9.29Jiuyang Liu
Update sbt-scalafix to 0.9.29
2021-06-04Update os-lib to 0.7.8Scala Steward
2021-06-04Update sbt-scalafix to 0.9.29Scala Steward
2021-06-04Rm java.io in FileUtilssinofp
2021-06-03Replace mem macros renaming (#2243)Albert Chen
* ReplaceMemMacros: add target rename test case * ReplaceMemMacros: rename references to instances * fix renaming for deduped mems * use grouped DummyAnnos to preserve order * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * run scalafmt * flatten targets Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-01Update sbt-scoverage to 1.8.1 (#2235)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-01Update scalatest to 3.2.9 (#2226)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-28remove testOnly, since upstream implemented it. (#2250)Jiuyang Liu
2021-05-28Merge pull request #2239 from scala-steward/update/sbt-scalafix-0.9.28Jiuyang Liu
Update sbt-scalafix to 0.9.28
2021-05-28Merge branch 'master' into update/sbt-scalafix-0.9.28Jiuyang Liu
2021-05-28Merge pull request #2248 from scala-steward/update/sbt-mima-plugin-0.9.2Jiuyang Liu
Update sbt-mima-plugin to 0.9.2
2021-05-26Update sbt-mima-plugin to 0.9.2Scala Steward
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen * Add CLI support for GenVerilogMemBehaviorModelAnno * Add simple test for GenVerilogMemBehaviorModelAnno * Fix for review 1. rename case class Port(prefix, `type`) to Port(prefix, portType) 2. fix AnnotatedMemoriesAnnotation collect function. 3. fix bug that ModuleName is not correct. * Format DumpMemoryAnnotations & ReplSeqMemTests * Fix for review 1. Inline genDecl, genPortSpec, genSequential, genCombinational 2. Add DefAnnotatedMemory informations in header 3. Change helpText 4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog * Fix ReadWritePort mask name Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-21Optimize Annotation.getTargets (#2244)Jack Koenig
2021-05-21Fix renaming of local targets in InlineInstances (#2238)Albert Chen
* add more inline renaming test cases * InlineInstances: fix renaming for local targets * run scalafmt Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-21Annotation: override getTargets for SingleTargetAnnotation (#2241)Kevin Laeufer
2021-05-21WiringTransform: cannot run after RemoveWires (#2240)Kevin Laeufer
2021-05-21Update sbt-scalafix to 0.9.28Scala Steward
2021-05-18Improve performance of RenameMap in LowerTypes (#2233)Jack Koenig
LowerTypes creates a lot of mappings for the RenameMap. The built-in .distinct of renames becomes a performance program for designs with deeply nested Aggregates. Because LowerTypes does not create duplicate renames, it can safely eschew the safety of using .distinct via a private internal API.
2021-05-18Add support for fat jars to benchmark_cold_compile.py (#2232)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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