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AgeCommit message (Expand)Author
2019-11-14Use getName instead of getSimpleNameSchuyler Eldridge
2019-11-14Add test with Transform inside objectSchuyler Eldridge
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-06Merge pull request #1206 from freechipsproject/issue-templatesSchuyler Eldridge
2019-11-06Add separate Issue and PR templatesSchuyler Eldridge
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
2019-11-05Bump to 1.3-SNAPSHOT (#1221)Jack Koenig
2019-11-05Merge pull request #1211 from freechipsproject/serialization-utilsDavid Biancolin
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
2019-10-31Merge pull request #1219 from freechipsproject/ifdef-initial-blockJack Koenig
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-31Merge pull request #1216 from freechipsproject/find-instsAlbert Magyar
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
2019-10-29Check that all annotations provide the typeHintDavid Biancolin
2019-10-29Try implementing recursive typeHint look upDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
2019-10-25Only emit the DeserilizationTypeHintsAnno when neededDavid Biancolin
2019-10-24Merge pull request #1208 from freechipsproject/comb-loop-error-infoAlbert Magyar
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
2019-10-24Add EdgeData trait to mix in to graphsAlbert Magyar
2019-10-24Supply a trait to allow user annotations to provide SERDES type hintsDavid Biancolin
2019-10-22Merge pull request #1204 from freechipsproject/else-ifSchuyler Eldridge
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
2019-10-22Emit Verilog "else if" in register updatesSchuyler Eldridge
2019-10-21Merge pull request #1202 from freechipsproject/fix-verilog-mem-delay-enAlbert Magyar
2019-10-21Add tests for memories with latency >1, toggling enablesAlbert Magyar
2019-10-21Add library for streamlined Verilog execution testsAlbert Magyar
2019-10-21Add test for #1179: comb-loops from VerilogMemDelaysAlbert Magyar
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-10-09Merge pull request #1199 from freechipsproject/top-wiring-idempotentSchuyler Eldridge
2019-10-08Add test for TopWiringTransform idempotencySchuyler Eldridge
2019-10-08Make TopWiringTransform idempotentSchuyler Eldridge
2019-10-07Absorb some instance analysis into InstanceGraph, use safer boxed Strings (#1...Albert Magyar
2019-10-03Add Block factory from argument list of Statements (#1197)Albert Magyar
2019-10-01Restore ResolveGenders to its status as a Pass (#1192)Jack Koenig
2019-10-01Merge pull request #1183 from freechipsproject/mem-read-under-writeAlbert Magyar
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-30Define read-write collison for independently clocked mem ports (#1188)Albert Magyar
2019-09-30Bump sbt to 1.3.2 (#1187)Jim Lawson
2019-09-25Add explicit hline instead of phantom h1 (#1189)Schuyler Eldridge
2019-09-19Faster inline renaming (#1184)Albert Chen
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