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2019-12-03Logger tweaks (#1190)edwardcwang
2019-11-29Merge pull request #1258 from freechipsproject/remove-old-loggerJack Koenig
Remove scala-logging fully in favor of our own logger
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
There was some vestigial logging that conflicts with the homebrewed logger used by most of the codebase
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
* Types containing bundles can't generally be converted to a single mask granularity * Update ReplSeqMemTests to check for illegal masks
2019-11-19Merge pull request #1245 from freechipsproject/auto-merge-backportsAlbert Magyar
[Mergify] Automatically merge backport PRs when ready
2019-11-18[Mergify] Drop review requirement for backport PRsAlbert Magyar
2019-11-18[Mergify] Automatically merge backport PRs when readyAlbert Magyar
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
* Closes #1242
2019-11-18Merge pull request #1231 from freechipsproject/automate-backportsAlbert Magyar
Use Mergify to automate backporting to 1.2.x
2019-11-18Merge branch 'master' into automate-backportsAlbert Magyar
2019-11-15Merge pull request #1228 from freechipsproject/getSimpleName-considered-harmfulJack Koenig
getSimpleName considered harmful
2019-11-14Use getName instead of getSimpleNameSchuyler Eldridge
This changes uses of `getSimpleName` to `getName`. The former throws idiotic exceptions under Java 8, e.g., `getSimpleName` will fail if used on a class inside an object. This fixes a bug where any call to the `name` method of a custom transform defined inside an object (or in an environment wrapping things in objects like a REPL) will throw a malformed class name exception. E.g., if you do this and run with `-ll info` or your custom transform deletes annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-14Add test with Transform inside objectSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
* Add spec for Analog type and attach statement * Describe role of attaches in partial connection algorithm * Change references that describe ground types where appropriate * Closes #1194 * Fix typo
2019-11-11Add labeling to Mergify backportingJack Koenig
2019-11-11Use Mergify to automate backporting to 1.2.xJack Koenig
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-06Merge pull request #1206 from freechipsproject/issue-templatesSchuyler Eldridge
Add separate Issue and PR templates
2019-11-06Add separate Issue and PR templatesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
Recursive literal lookup needs to be guarded against combinational loops Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
2019-11-05Bump to 1.3-SNAPSHOT (#1221)Jack Koenig
2019-11-05Merge pull request #1211 from freechipsproject/serialization-utilsDavid Biancolin
Supply a trait to allow user annotations to provide JsonProtocol type hints
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
* Fixes #1154 * Tests that #1154 example produces SyntaxErrorsException * Generally helps catch trailing syntax errors * Performance-neutral relative to previous grammar * Recommended by antlr4 devs, can help performance in some cases * See antlr/antlr4#1540
2019-10-31Merge pull request #1219 from freechipsproject/ifdef-initial-blockJack Koenig
Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-31Merge pull request #1216 from freechipsproject/find-instsAlbert Magyar
Change findInstancesInHierarchy to return implicit top instance
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
Co-Authored-By: Jack Koenig <koenig@sifive.com>
2019-10-29Check that all annotations provide the typeHintDavid Biancolin
2019-10-29Try implementing recursive typeHint look upDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
* Change FIRRTL-internal API, affecting only one corner case * Make API more "DWIM" and consistent with other methods * Add test cases for findInstancesInHierarchy * Update Scaladoc
2019-10-25Only emit the DeserilizationTypeHintsAnno when neededDavid Biancolin
2019-10-24Merge pull request #1208 from freechipsproject/comb-loop-error-infoAlbert Magyar
Enhance CheckCombLoops errors with connection info
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
* Closes #1203
2019-10-24Add EdgeData trait to mix in to graphsAlbert Magyar
* Add Scaladoc for EdgeData API * Include stringified vertices in EdgeNotFoundException
2019-10-24Supply a trait to allow user annotations to provide SERDES type hintsDavid Biancolin
2019-10-22Merge pull request #1204 from freechipsproject/else-ifSchuyler Eldridge
Emit Verilog else-if for Register Updates
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-22Emit Verilog "else if" in register updatesSchuyler Eldridge
Modifies the Verilog emitter to emit "else if" blocks as opposed to more deeply nested "else begin if" blocks. This improves the output Verilog readability. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Merge pull request #1202 from freechipsproject/fix-verilog-mem-delay-enAlbert Magyar
Fix handling of read enables for write-first (default) memories in VerilogMemDelays
2019-10-21Add tests for memories with latency >1, toggling enablesAlbert Magyar
2019-10-21Add library for streamlined Verilog execution testsAlbert Magyar
2019-10-21Add test for #1179: comb-loops from VerilogMemDelaysAlbert Magyar
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
* Additional refactoring to clean up pass implementation * Make register names match old scheme to appease CI
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-10-09Merge pull request #1199 from freechipsproject/top-wiring-idempotentSchuyler Eldridge
Make TopWiringTransform Idempotent
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