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AgeCommit message (Expand)Author
2020-07-29RemoveWires: improve dependencies and declare ResolveKinds as an invalidation...Kevin Laeufer
2020-07-29InferTypes: fix bugs with unknown widths on ports and memories (#1769)Kevin Laeufer
2020-07-29RenameMapSpec: try rename instance and port (#1776)Kevin Laeufer
2020-07-28Fix incorrect error message (#1795)Andrew Waterman
2020-07-27Merge pull request #1528 from freechipsproject/conditionally-scopesAlbert Magyar
2020-07-27Fix out-of-scope reference in handwritten CHIRRTL mem testAlbert Magyar
2020-07-27Add adapter to make current CHIRRTL mport scoping legalAlbert Magyar
2020-07-27Add Conditionally scoping tests to CheckSpecAlbert Magyar
2020-07-27Honor block scoping of Conditionally in CheckHighFormAlbert Magyar
2020-07-27Update RightShiftTests.fir to avoid buggy Counter patternAlbert Magyar
2020-07-27Add Treadle publishLocal to CI for Chisel3 Tests (#1793)Schuyler Eldridge
2020-07-25Integrate new transforms with firrtl.stage.Forms (#1754)Schuyler Eldridge
2020-07-24Fix sign extension issue in Emitter (#1785)Albert Chen
2020-07-23fix reduction op bug ConstantPropagation (#1746)Albert Chen
2020-07-23mask bits when propagating bitwise ops (#1745)Albert Chen
2020-07-23Update negative literal emission (#1782)Albert Chen
2020-07-20Make InferWidths thread safe (#1775)Schuyler Eldridge
2020-07-18Faster dedup instance graph (#1732)Kevin Laeufer
2020-07-17Cross-build unidoc in CI (#1772)Schuyler Eldridge
2020-07-17Merge pull request #1771 from freechipsproject/fuzzer-2.11-fixesSchuyler Eldridge
2020-07-17Fix Fuzzer for 2.11Schuyler Eldridge
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
2020-07-16Add Expression Fuzzer (#1741)Albert Chen
2020-07-16Merge pull request #1753 from freechipsproject/rm-duplicate-testsSchuyler Eldridge
2020-07-16Simplify CustomTransformSpecSchuyler Eldridge
2020-07-16Remove overlapping inputForm=LowForm testsSchuyler Eldridge
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
2020-07-14Make TopWiringTransform run before LowerTypes (#1750)Schuyler Eldridge
2020-07-14Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-07-14Remove scalastyle configs from repositoryAlbert Magyar
2020-07-14Fix parsing of info on multi-line registers (#1735)Jack Koenig
2020-07-13[spec] Specify execution order of side-effect-having statements (#1724)Albert Magyar
2020-07-13Change ProtoBuf generated directory (#1762)Jack Koenig
2020-07-13add .bloop and .metals to .gitignore (#1761)Albert Chen
2020-07-10Remove Left Over References to Gender in Code (#1752)Kevin Laeufer
2020-07-09[spec] Explicitly disallow shadowing of component names (#1749)Albert Magyar
2020-07-08dedup: use structural sha256 hash instead of agnostify and serialize (#1731)Kevin Laeufer
2020-07-08ir: add faster serializer (#1694)Kevin Laeufer
2020-07-07verification: emit mesage as Verilog comment (#1712)Kevin Laeufer
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-26Add test for ConvertAssertsAlbert Magyar
2020-06-26Add ConvertAsserts transform to map asserts to Verilog-friendly nodesAlbert Magyar
2020-06-25Batch renames in LowerTypes (#1718)Schuyler Eldridge
2020-06-25Merge pull request #1638 from freechipsproject/manipulate-names-issues-refactorSchuyler Eldridge
2020-06-25Add --change-name-case <lower|upper> optionSchuyler Eldridge
2020-06-25Test both LowerCaseNames and UpperCaseNamesSchuyler Eldridge
2020-06-25Add LetterCaseTransformsSchuyler Eldridge
2020-06-25Add a second instance to Verilog keyword testSchuyler Eldridge
2020-06-25Test ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
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