aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2021-04-28Update sbt to 1.3.13 (#1730)Scala Steward
2021-04-28Update sbt-protobuf to 0.7.0 (#2134)Scala Steward
2021-04-28Update sbt-ci-release to 1.5.7 (#2148)Scala Steward
2021-04-28Update sbt-scalafix to 0.9.27 (#2161)Scala Steward
2021-04-28Update antlr4, antlr4-runtime to 4.9.2 (#2137)Scala Steward
2021-04-28Update sbt-scoverage to 1.7.0 (#2204)Scala Steward
2021-04-28Update scala-parallel-collections to 1.0.2 (#2163)Scala Steward
2021-04-28Update scalatest to 3.2.8 (#2194)Scala Steward
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
2021-04-19Update .mergify.yml (#2181)github-actions[bot]
2021-04-19Hoist Transform timing to the Phase level (#2190)Jack Koenig
2021-04-19Simplify "update .mergify.yml" workflow (#2192)Jack Koenig
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-16Fix signedness of xor const prop with zero (#2179)Fabian Schuiki
2021-04-15Add Workflow to automatically update .mergify.yml (#2180)Jack Koenig
2021-04-13Add indent parameter to Serializer.serialize() (#2177)Jared Barocsi
2021-04-11smt: use existing bitWidth API (#2175)edwardcwang
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
2021-04-05Merge pull request #2111 from chipsalliance/fpga-backendAlbert Magyar
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-04Fix mill cache download (#2171)Jiuyang Liu
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-30Fix Mill support for non-M1 Macs (#2165)Jack Koenig
2021-03-30Update README.md (#2164)Jack Koenig
2021-03-30don't use protoc-jar anymore, mill can handle it better. (#2162)Jiuyang Liu
2021-03-29Update protobuf-java to 3.15.6 (#2136)Scala Steward
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
2021-03-25add scalafmt to mill (#2151)Jiuyang Liu
2021-03-22Fix mill compile and add to CI (#2147)Jiuyang Liu
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-17 09:04:46 +0000