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2020-05-06Clarify spec indentation of when/elseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Clarify indentation in specSchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Update sbt-scalafix to 0.9.15 (#1536)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-06Update sbt to 1.3.10 (#1529)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-06Update moultingyaml to 0.4.2 (#1480)Scala Steward
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-06Update protoc-jar to 3.11.4 (#1434)Scala Steward
Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-06Update scalatest to 3.1.1 (#1405)Scala Steward
* Update scalatest to 3.1.1 * Update scalatest to 3.1.1 * Update scalatest to 3.1.1 Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-05before/after initial block macros (#1550)Deborah Soung
* adding init macros * fix missing tick * adding more documentation; fixing up emitter tests * adding initial-guarding macro test * prefixing macros with FIRRTL * cleanup * typo fix Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-05add Firrtl plugin info for intellij platform (#1547)XinJun Ma
2020-05-04Merge pull request #1556 from freechipsproject/legalize-andreduceSchuyler Eldridge
Add LegalizeAndReductionsTransform
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
Workaround for https://github.com/verilator/verilator #2300 present in Verilator versions v4.026 - v4.032. This transform turns AND reductions for expressions > 64-bits into an equality check with all ones. It is included as a prerequisite for all Verilog emitters.
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
This adds missing invalidations to four transforms: - ExpandConnects - RemoveAccesses - SplitExpressions - VerilogMemDelays This necessarily updates test cases which expect exact transform orders to reflect the new order. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-01Emitter: guard _RAND_* declarations with ifdef (#1548)Albert Chen
* Emitter: add declare functions ifdef guard * Emitter: add ifdef initials * Emitter: add comments, cleanup * Emitter: changes from code review - make new methods private - use .withDefault - remove empty initial block Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-30Update Mergify rules to backport to 1.3.x (#1552)Jack Koenig
This replaces the rules for 1.2.x
2020-04-27Fix remaining 'removed in 1.3' deprecations (#1542)Albert Magyar
* Bump old 'removed in 1.3' deprecation * Remove outdated passes.VerilogRename * Fixes #1467
2020-04-22Merge pull request #1537 from freechipsproject/optionalPrerequisitesOfSchuyler Eldridge
Change `dependents` to `optionalPrerequisiteOf`
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add optionalPrerequisiteOf, deprecate dependentsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Merge pull request #1534 from freechipsproject/deprecate-transform-2Schuyler Eldridge
Trait-base Dependency API Migration
2020-04-22Avoid repeated set construction in WiringTransform invalidatesSchuyler Eldridge
Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add ExpandPrepares wrapperSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add IdentityLike mix-in for TransformLikeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add trait-based Dependency API migration pathSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Use private LinkedHashSets in DependencyManagerSchuyler Eldridge
Changes the DependencyManager to use the private[options] LinkedHashSet members that shadow the public Seq[_] dependencies. This should avoid some unnecessary set construction and also improves readability of the DependencyManager code. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Fix typo in private DependencyAPI memberSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Add test cases for illegal casts to AsyncReset / ClockAlbert Magyar
2020-04-20Remove repetitive pass lists from WidthTestsAlbert Magyar
2020-04-20Avoid using infix for mutable append in CheckWidthsAlbert Magyar
2020-04-20Ensure arguments to asClock / asAsyncReset are single-bitAlbert Magyar
2020-04-20Avoid casting 2-bit interval to AsyncReset in testAlbert Magyar
2020-04-14Merge pull request #1525 from freechipsproject/async-self-init-supportedJack Koenig
Prevent infinite recursion in CheckResets
2020-04-14Add Paul's async-reset self-init case as a testAlbert Magyar
2020-04-14Avoid infinite loops on async-reset self-inits in CheckResetsAlbert Magyar
* Fixes #1516 * Tighten up logic for "casted literal" checking
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
Chisel emits all literals as UInts cast to the correct type, make CheckResets support casts when checking that async reset registers are reset to literal values. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Add new test jar to .gitignore (#1520)Albert Magyar
2020-04-13Add test-case for explicit padding of SInts in mverilog compilerAlbert Magyar
2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-13Merge pull request #1512 from freechipsproject/issue-1511Schuyler Eldridge
Fix mixed -E and -e emission
2020-04-13Add test of mixing -e with -E in FirrtlMainSpecSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Check EmitAnnotation class before emittingSchuyler Eldridge
Fixes a bug where an Emitter was only checking for the presence of an EmitCircuitAnnotation or EmitAllModulesAnnotation to control its emission flavor (one-file-per-module or one-file). This changes the check to ensure that the class of emitter matches that of the annotation. This allows for correct behavior when mixing different emitters, e.g., -E high -e middle. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Split Checks into separate filesAlbert Magyar
2020-04-13Split Resolves into separate filesAlbert Magyar
* Remove unused imports
2020-04-13move asyncInitials inside initial block RANDOMIZE ifdef (#1510)John Ingalls
2020-04-13[spec] Add Fixed to spec (#1456)Albert Magyar
* [spec] Add Fixed to spec * Fixes #1195 * Define type & parameters * Add Fixed as argument type to type conversions * Add Fixed as argument type to relevent PrimOps (with link to tables) * Add asFixed PrimOp * Add IncP/DecP/SetP primops * Add fixed-point width/point propagation tables * Update spec pdf Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-11EliminateTargetPaths: don't duplicate modules with only one instance (#1504)Albert Chen
* EliminateTargetPaths: add lone instance test cases * EliminateTargetPaths: don't rename lone instances * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Split Passes.scala into separate files (#1496)Adam Izraelevitz
* Split Passes.scala into separate files * Add imports of implicit things Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Add ground type serializer (#1502)Albert Chen
* update JsonProtocolSpec to test GroundType * add custom serializer for GroundType * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Support infoMode for Strings (#782)edwardcwang
* Support infoMode for Strings It seemed like an API hole that I couldn't use infoMode with a string but had to manually create an iterator first. * Fix build error Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
* Fix dynamic SubAccess of zero-length vectors * Fixes #230 * Add new ZeroLengthVecs pass that occurs before RemoveAccesses * Include this in stage.Forms.MidForm * Add to High->Mid order in compiler test based on @seldridge feedback * Use validif to produce out-of-bounds value in ZeroLengthVecs * Update scaladoc * Fix test imports
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