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need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala
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there yet. Will allow simple bulk connecting at top-level
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updated Makefile to play nicer when firrtl is a submodule, fixed bug in Translator for single line scopes, fixed firrtl-scala script to point to firrtl.Driver instead of old firrtl.Test
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support for -b <backend> flag without any other specified passes in stanza, updated parser tests to work with stanza implementation.
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backend can be applied. Added firrtl compiler for emitting firrtl
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Conflicts:
Makefile
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Updated Scala FIRRTL with Testing and Infer-Types Pass
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convert object <=> string, added eqv and neqv
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modified Logger slightly, added Primops object for utility functions, minor changes in Utils
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sense for some applications, also fixed up printing to better match stanza implementation
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printing to match stanza implementation
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of printVars still missing. Added Logger class for debug printing
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for unknown width. Also added test to check this
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This way I don't have to type "make install-linux" whenever a new
Stanza zip drops.
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Changed DefMemory to be a non-vector type with a size member
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Conflicts:
README.md
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Add Scala implementation to firrtl repo
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AST -> String). Uses ANTLRv4 to generate concrete syntax parser
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Change of FIRRTL semantics!
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Fix init accessor
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ASIC backend.
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Assignments to a register are no longer affected by enclosing when
statements:
when p :
reg r : UInt,clk,reset
r := a
will lower to:
reg r : UInt,clk,reset
r := a
instead of:
reg r : UInt,clk,reset
when p : r := a
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StandardVerilogCompiler
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Make Link.fir reference relative path
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particular directory structure.
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catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
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