| Age | Commit message (Expand) | Author |
|---|
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Updated flo backend | azidar |
| 2015-07-14 | Passes riscv-mini tests | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Added chisel feedback to firrtl spec. Datapath_new triggers too large a width... | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | Partial commit | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-14 | Fixed bug in lowering, where the indexes to many-connects and accessors weren... | azidar |
| 2015-07-06 | Updated todo | azidar |
| 2015-07-02 | Added firrtl-lexer | azidar |
| 2015-07-02 | Fixed performance bugs, runs 7x faster | azidar |
| 2015-07-02 | Fixed stanza, optimize works, added a time printout | azidar |
| 2015-07-02 | Hopefully fixed stanza so it can correctly compile itself | azidar |
| 2015-07-01 | Updated TODO. | azidar |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar |
| 2015-06-29 | Fixed minor typos. As of now, the finished version for internal feedback. | azidar |
| 2015-06-26 | Changed clock from port kind to type | azidar |
| 2015-06-26 | Finished draft of Version 0.1.3. Ready for comments. | azidar |
| 2015-06-23 | More updates to spec | azidar |
| 2015-06-22 | Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors | azidar |
| 2015-06-12 | Added more changes to spec | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-05 | Added updated stanza | azidar |
| 2015-06-05 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-06-05 | Added most recent pdf | azidar |
| 2015-06-05 | Commited most recent pdf | azidar |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to gene... | azidar |
| 2015-06-04 | Added Adam's changes to stanza | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Added low firrtl check. Corrected bug in prefix matching in high firrtl check | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-06-02 | Merge pull request #11 from jackbackrack/master | Adam Izraelevitz |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-06-02 | turn off eliminate-temps until improved | jackbackrack |
| 2015-06-02 | merge + fix trim to use correct bits operands | jackbackrack |
| 2015-05-29 | fix concat, as-sint, turn off temp-elimination | jackbackrack |
| 2015-05-29 | Fixed bugs in when-coverage pass. Works but has not been thoroughly tested | azidar |
| 2015-05-29 | Added new stanza | azidar |
| 2015-05-29 | Added custom pass. Does not correctly run, stanza just spins. Requires debugg... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-21 | fix pad/trim pass and fix bug in bits-select width inference | jackbackrack |
| 2015-05-21 | Added pad pass, used for flo backend | azidar |
| 2015-05-20 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-05-20 | Merge pull request #9 from jackbackrack/master | Adam Izraelevitz |
