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2015-07-21Updated TODOazidar
2015-07-16Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
Conflicts: src/main/stanza/firrtl-ir.stanza src/main/stanza/passes.stanza src/main/stanza/verilog.stanza
2015-07-16Fixed rename to work with chisel3 stuffazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Updated flo backendazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Added chisel feedback to firrtl spec. Datapath_new triggers too large a ↵azidar
width error
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14Partial commitazidar
2015-07-14In progress commitazidar
2015-07-14Fixed bug in lowering, where the indexes to many-connects and accessors ↵azidar
weren't lowered
2015-07-13Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-10Added clock supportazidar
2015-07-07Updated flo backendazidar
2015-07-07Passes riscv-mini testsazidar
2015-07-07Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-06Added chisel feedback to firrtl spec. Datapath_new triggers too large a ↵azidar
width error
2015-07-06Still partial commit, many tests pass. Many tests fail.azidar
2015-07-06Partial commitazidar
2015-07-06In progress commitazidar
2015-07-06Updated todoazidar
2015-07-02Added firrtl-lexerazidar
2015-07-02Fixed performance bugs, runs 7x fasterazidar
2015-07-02Fixed stanza, optimize works, added a time printoutazidar
2015-07-02Hopefully fixed stanza so it can correctly compile itselfazidar
2015-07-01Updated TODO.azidar
2015-06-30Updated TODO. Ran spelling/grammar check on specazidar
2015-06-29Fixed minor typos. As of now, the finished version for internal feedback.azidar
2015-06-26Changed clock from port kind to typeazidar
2015-06-26Finished draft of Version 0.1.3. Ready for comments.azidar
2015-06-23More updates to specazidar
2015-06-22Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessorsazidar
2015-06-12Added more changes to specazidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-05Added updated stanzaazidar
2015-06-05Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-06-05Added most recent pdfazidar
2015-06-05Commited most recent pdfazidar
2015-06-04Fixed fir files so they correctly compile to verilog! Front-end needs to ↵azidar
generate as-SInt instead of convert, always. Added fast build to Makefile
2015-06-04Added Adam's changes to stanzaazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Added low firrtl check. Corrected bug in prefix matching in high firrtl checkazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵azidar
low-firrtl syntax. Generates verilog that compiles, but is not correct
2015-06-02Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-06-02Merge pull request #11 from jackbackrack/masterAdam Izraelevitz
fix pad/trimming pass and fix bits-select width inference bug
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-06-02turn off eliminate-temps until improvedjackbackrack
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