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AgeCommit message (Expand)Author
2016-01-20WIP: finished partial connectazidar
2016-01-19WIP: Writing new spec.azidar
2016-01-17Forgot to add the changesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ...azidar
2016-01-17Added check for uint on access index typeazidar
2016-01-17Removed temporary filesazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Standard Verilog doesn't use Resolve(), but lists out the resolution passes i...azidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
2016-01-16Fixed bug in lowering memories that had aggregate data typesazidar
2016-01-16Fixed bug in check-init that allows it to check on non-lowered thingsazidar
2016-01-16Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat...azidar
2016-01-16Nodes must now be ground typesazidar
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Fixed Vector performance testsazidar
2016-01-16Reworked Verilog emission of registers to if/else instead of ?:azidar
2016-01-16No longer split on muxesazidar
2016-01-16Commented back in Starting and Finishing for testingazidar
2016-01-16Sped up remove access by checking a conditionazidar
2016-01-16Added more data in printout of time to compileazidar
2016-01-16printf no longer includes a new lineazidar
2016-01-16Verilog emission no longer casts input to shr or bit selectazidar
2016-01-16Added hashed on get flipazidar
2016-01-16Sped up some passes. Added global mname to allow easy per-module hashes for a...azidar
2016-01-16Made create-exps a bit fasterazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks t...azidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16Added src and test filesazidar
2016-01-16WIP adding chirrtlazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...azidar
2016-01-16WIP getting through testsazidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass al...azidar
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about emitt...azidar
2016-01-16WIP. Compiles and there's some outputazidar
2016-01-16WIP. Compiles, need to testazidar
2016-01-16WIPazidar
2016-01-16Added memory thoughtsazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Merge branch 'scala' of github.com:ucb-bar/firrtlazidar
2016-01-16Added some commentsazidar
2016-01-16Added performance testsazidar
2016-01-16Printf no longer adds a new lineazidar
2016-01-16shift right does not cast input as signedazidar
2016-01-16Extraction inputs are no longer castazidar
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