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2021-02-01Suport ir.SubAccess in Utils.splitRef (#2021)Schuyler Eldridge
* Add SubAccess case to Utils.splitRef Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Update Utils.splitRef to use IR types Change Utils.splitRef to use the actual IR types instead of their WIR aliases. Update the Scaladoc note to reflect this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
* Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-01ConstantPropagation: make RemoveValidIf an optional dependency (#2027)Kevin Laeufer
This allows ConstantPropagation to be used in cases where ValidIfs need to be maintained, e.g., in the formal backend. Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
Fixes bug with mul or div followed by cat. Also fixes some Verilog lint issues.
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
* Check Unidoc on all versions of Scala It is required for publishing and we publish every version * Fix conflicting cross-version suffixes issue When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version for the fuzzer and benchmark projects even though they aren't really relevant to the command. This may be a misconfiguration or a bug in the unidoc plugin. Whatever the case, simply making it possible for them to use the same version of Scala as the firrtl project (on which they depend) fixes the issue. * Match versions of Scala in build.sbt and CI * Fix unidoc issues in 2.13.4 There is some bug in ScalaDoc not finding some links in firrtl.options so those links were made absolute as a workaround.
2021-01-22Bump to Scala 2.12.13 and 2.13.4 (#2053)Jack Koenig
2021-01-20Cleanup some warnings (#2032)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-20Add --dont-fold option to disable folding prim ops (#2040)Schuyler Eldridge
This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-01-19Restore scalafmt CI check (#2047)Jack Koenig
Fix scalafmtCheckAll failures that snuck through
2021-01-19Fix Mergify condition for labeling backports (#2048)Jack Koenig
2021-01-19smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)Kevin Laeufer
2021-01-19Switch from Travis to Github Actions CI (#2041)Jack Koenig
* Fix .run_formal_checks for Github Actions instead of Travis * Remove .run_chisel_tests Because we publish SNAPSHOTs on every merge to master, the Chisel repo checks against master of FIRRTL regularly * Only run unidoc for Scala 2.12 Under Travis we ran for 2.11, 2.12, and 2.13, but it doesn't work when using ++2.<major>.<minor> when major != to 2.12. It seems if we want to run all 3, we have to run as `sbt +unidoc`. It's not clear how much benefit we get from building on the other versions, so stick with 2.12 for now. * Generate .mergify.yml with script in chisel-repo-tools Generated with config: conditions: - status-success=all tests passed branches: - 1.2.x - 1.3.x - 1.4.x
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
This is done by having LowerTypes uses two RenameMaps instead of one for each module. There is one for renaming instance paths, and one for renaming everything within modules. Also add some utilities: * TargetUtils for dealing with InstanceTargets * RenameMap.fromInstanceRenames
2020-12-11fix scaladoc for ReferenceTarget (#2014)Megan Wachs
2020-12-10Add newline in the end of LoFIRRTL file (#2015)XinJun Ma
2020-12-07Fix Mergify badge in README (#1974)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-04Remove explicit pom scm from build.sbt (#2004)Jack Koenig
This is now set by sbt-ci-release
2020-12-03Restore publish settings to before sbt-ci-release (#1999)Jack Koenig
sbt-ci-release changes the commands required to publish to Sonatype. While this may be a desirable change at some point, it is inconsistent with other repos. Reverting for the time being.
2020-12-02smt: add support for uninterpreted ext modules (#1994)Kevin Laeufer
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-02Fix subaccess (#1984)Jiuyang Liu
* add test for RemoveAccessesSpec. * fix nested SubAccess bug. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-30Add SortModules Transform (#1905)Schuyler Eldridge
* Add SortModules to transform to def-before-use Adds a new transform, SortModules, that transforms a FIRRTL circuit to enforce an invariant of modules and external modules being defined before use. This transform is left as optional in the event that a user may wish to have a quick way of getting the circuit to respect this property as may be expected of some other tool, e.g., MLIR. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of SortModules transform Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-23add weak and strong to Utils.v_keywords (#1983)Tim Snyder
Verilator 4.034 was complaining about wires being named weak and strong because those are SV 2009 keywords. Added them to the Utils.v_keywords list
2020-11-17Make MultiTargetAnnotation.targets a def (#1969)Jack Koenig
* Make MultiTargetAnnotation.targets a def This enables the annotation writer to choose their own underlying data structure * Update MultiTargetAnnotation ScalaDoc Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-17Fix Type Error fuzzer Example code (#1960)JADE KIM
Seq[(Int, DoPrimGen)] to Map[ExprGen[_ <: Expression], Int]
2020-11-16bump antlr4 (#1936)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-16make LazyLogging log to console by default. (#1961)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-16Switch to allowlist in Travis SNAPSHOT publishing (#1962)Jack Koenig
2020-11-12Automatically publish SNAPSHOTs on pushes to master (#1955)Jack Koenig
Uses sbt-ci-release for automation
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
It would replace them with a validif node with a UIntLiteral which can lead to type errors.
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Bump SNAPSHOT version (#1947)Jack Koenig
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
* smt: add test for write port collision * smt: add missing call to insertDummyAssignsForMemoryOutputs * smt: fix typo in write port code Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-10Refactor emiter (#1879)Jiuyang Liu
* split big Emitter to submodules. * fix all deprecated warning. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
* smt: add tests for assert name clashes * smt: ensure unique signal names with a namespace this fixes issues #1934
2020-11-07-full64 is required to detect VCS. (#1930)Jiuyang Liu
2020-11-04Remove caching from RenameMap (#1938)Jack Koenig
2020-11-04Add 1.4.x to Mergify (#1920)Jack Koenig
2020-10-27Merge pull request #1932 from freechipsproject/fix_VerilogPrepJiuyang Liu
Fix verilog prep
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26bug fix for VerilogPrep using wrong type.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-13Make {Stage, FirrtlStage}.run protected (#1926)Schuyler Eldridge
* Make Stage.run protected Change the access modifier of Stage.run from no modifier to protected. This method is really an internal API that the user implements with the main entry point for a Stage being "execute" or "transform". By allowing users to access "run" they can bypass checks, mandatory file reads/writes, and wrappers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Make FirrtlStage.run protected Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-12Update junit to 4.13.1 (#1925)Scala Steward
2020-10-05Merge pull request #1915 from freechipsproject/fix-negative-literal-fixupJack Koenig
Fix "fix" for negative literals > 32 bits
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
Overflow of 32-bit Int would cause any negative literal value equal to -(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
2020-09-30Merge pull request #1908 from freechipsproject/fix-direct-mem-to-mem-connsAlbert Magyar
VerilogMemDelays: fix lowering of direct mem-to-mem connections
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
* Also clean up VerilogMemDelaySpec structure
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-30Speed up writing CustomFileEmission with buffering (#1906)Jack Koenig
Also speed up common case of Array[Byte]
2020-09-28License reference in maven publishing info (#1907)Chick Markley
now points to apache 2.0
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