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InferWidths now only fixes declaration widths
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Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206 and #200.
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Added future-release.txt
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Rework Annotations
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Conflicts:
src/main/scala/firrtl/Compiler.scala
src/main/scala/firrtl/LoweringCompilers.scala
src/main/scala/firrtl/passes/Inline.scala
src/test/scala/firrtlTests/AnnotationTests.scala
src/test/scala/firrtlTests/InlineInstancesTests.scala
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Fixed reg concrete syntax. #197.
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Keeps track of proposed changes to add to the next version of the Firrtl spec.
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Added a Chirrtl check for undeclared wires, etc.
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Detects and flags cyclic module loops
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Removed InferWidths after ExpandWhens
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Indentation support for the ANTLR parser
- some clean-up of the parser code (TODO: file input could be improved, more clean-up)
- get rid of Translator and specify all syntactic rules in antlr4 grammer
- support for else-when shorthand in the grammar
- rename Begin to Block which makes more sense
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Randomization should be controllable separately. Verilator, for
example, already does this if it is passed --x-assign unique; doing
it redundantly reduces simulation performance.
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This approach uses the normal Unix mechanisms, rather than log grepping.
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printf: support '%c' for printing characters
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This allows for testbench handling of pipelined reset,
independently of `PRINTF_COND.
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- Based upon stop value, use $fatal instead of $finish. This causes
the Verilog simulator to signal an error to the OS as appropriate.
- Don't guard stop with `PRINTF_COND (only not-`SYNTHESIS).
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Ir cleanup fix
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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Add simple documentation
trait PrimOp -> abstract class PrimOp
Move PrimOp case objects to object PrimOps
Rename PrimOp case objects to match concrete syntax
Overrwrite toString for more canonical serialization
Update some PrimOps utility functions
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trait Expression -> abstract class Expression
Ref -> Reference
abbrev. exp -> expr
Add abstract class Literal
UIntValue -> UIntLiteral extends Literal
SIntValue -> SIntLiteral extends Literal
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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Add simple documentation
trait Width -> abstract class Width
case class UnknownWidth -> case object UnknownWidth
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Add simple documentation
Flip -> Orientation
trait Orientation -> abstract class Orientation
Orientation case objects to upper camel case
REVERSE -> Flip
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trait Type -> abstract class Type
case class ClockType() -> case object ClockType
case class UnknownType() -> case object UnknownType
Add GroundType and AggregateType
ClockType has width of IntWidth(1)
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Add simple documentation
Change Direction case objects to upper camel case
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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In 7afe9f6180a53fd9f024c67d78289689a601c8b7, I reintroduced a performance
pathology when recursing through Mux trees. This patch prevents
redundantly expanding the same Mux more than a constant number of times,
preserving linear runtime but still resulting in acceptable QoR.
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Add test to check compiler is thread safe
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Previously, we emitted if-else sequences for reg updates. Recent
improvements to FIRRTL resulted in the emission of explicit mux
networks instead. While equivalent, doing so reduces QoR, presumably
because ECAD tools are tuned to the habits of manual Verilog coders.
This seems to be a result of WRefs appearing between the regs and muxes.
Chasing down the sources of the WRefs corrects the code generation.
This patch reduces the Rocket pipeline area by about 2% and improves
rocket-chip's Verilator performance by about 8%.
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Fixes #187.
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Updated spec
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Suppress "match may not be exhaustive" warning
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Fix for bug introduced in #174
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